scholarly journals A Study about Schottky Barrier Height and Ideality Factor in Thin Film Transistors with Metal/Zinc Oxide Nanoparticles Structures Aiming Flexible Electronics Application

Nanomaterials ◽  
2021 ◽  
Vol 11 (5) ◽  
pp. 1188
Author(s):  
Ivan Rodrigo Kaufmann ◽  
Onur Zerey ◽  
Thorsten Meyers ◽  
Julia Reker ◽  
Fábio Vidor ◽  
...  

Zinc oxide nanoparticles (ZnO NP) used for the channel region in inverted coplanar setup in Thin Film Transistors (TFT) were the focus of this study. The regions between the source electrode and the ZnO NP and the drain electrode were under investigation as they produce a Schottky barrier in metal-semiconductor interfaces. A more general Thermionic emission theory must be evaluated: one that considers both metal/semiconductor interfaces (MSM structures). Aluminum, gold, and nickel were used as metallization layers for source and drain electrodes. An organic-inorganic nanocomposite was used as a gate dielectric. The TFTs transfer and output characteristics curves were extracted, and a numerical computational program was used for fitting the data; hence information about Schottky Barrier Height (SBH) and ideality factors for each TFT could be estimated. The nickel metallization appears with the lowest SBH among the metals investigated. For this metal and for higher drain-to-source voltages, the SBH tended to converge to some value around 0.3 eV. The developed fitting method showed good fitting accuracy even when the metallization produced different SBH in each metal-semiconductor interface, as was the case for gold metallization. The Schottky effect is also present and was studied when the drain-to-source voltages and/or the gate voltage were increased.

2012 ◽  
Vol 24 (18) ◽  
pp. 3517-3524 ◽  
Author(s):  
Song Yun Cho ◽  
Young Hun Kang ◽  
Jun-Young Jung ◽  
So Youn Nam ◽  
Jongsun Lim ◽  
...  

2019 ◽  
Vol 9 (23) ◽  
pp. 5014
Author(s):  
Courtin ◽  
Moréac ◽  
Delhaye ◽  
Lépine ◽  
Tricot ◽  
...  

Fermi level pinning at metal/semiconductor interfaces forbids a total control over the Schottky barrier height. 2D materials may be an interesting route to circumvent this problem. As they weakly interact with their substrate through Van der Waals forces, deposition of 2D materials avoids the formation of the large density of state at the semiconductor interface often responsible for Fermi level pinning. Here, we demonstrate the possibility to alleviate Fermi-level pinning and reduce the Schottky barrier height by the association of surface passivation of germanium with the deposition of 2D graphene.


2012 ◽  
Vol 521 ◽  
pp. 141-151
Author(s):  
Stephen J. Pearton ◽  
Wan Tae Lim ◽  
Erica Douglas ◽  
Hyun Cho ◽  
F. Ren

There is increasing interest in use of conducting oxide materials in new forms of transparent, flexible or wearable electronics on cheap substrates, including paper. While Si-based thin film transistors (TFTs) are widely used in displays, there are some drawbacks such as light sensitivity and light degradation and low field effect mobility (<1 cm2/Vs). For example, virtually all liquid crystal displays (LCDs) use TFTs imbedded in the panel itself. One of the promising alternatives to use of Si TFTs involves amorphous or nanocrystalline n-type oxide semiconductors. There have been promising results with zinc oxide, indium gallium oxide and zinc tin oxide channels. In this paper, recent progress in these new materials for TFTs on substrates such as paper is reviewed. In addition, InGaZnO transistor arrays show promise for driving laminar electroluminescent, organic light-emitting diode (OLED) and LCD displays. These transistors may potentially operate at up to an order of magnitude faster than Si TFTs. We have fabricated bottomgate amorphous (α-) indium-gallium-zinc-oxide (InGaZnO4) thin film transistors (TFTs) on both paper and glass substrates at low processing temperature (≤100°C). As a water and solvent barrier layer, cyclotene (BCB 3022-35 from Dow Chemical) was spin-coated on the entire paper substrate. TFTs on the paper substrates exhibited saturation mobility (μsat) of 1.2 cm2.V-1.s-1, threshold voltage (VTH) of 1.9V, subthreshold gate-voltage swing (S) of 0.65V.decade-1, and drain current onto- off ratio (ION/IOFFSubscript text) of ~104. These values were only slightly inferior to those obtained from devices on glass substrates (μsat~2.1 cm2.V-1.s-1, VTH ~0 V, S~0.74 V.decade-1, and ION/IOFF=105- 106). The uneven surface of the paper sheet led to relatively poor contact resistance between source-drain electrodes and channel layer. Future areas for development are identified.


2011 ◽  
Vol 519 (15) ◽  
pp. 5208-5211 ◽  
Author(s):  
W.K. Lee ◽  
K.C. Aw ◽  
H.Y. Wong ◽  
K.Y. Chan ◽  
M. Leung ◽  
...  

2013 ◽  
Vol 102 (24) ◽  
pp. 242114 ◽  
Author(s):  
Sejoon Lee ◽  
Youngmin Lee ◽  
Deuk Young Kim ◽  
Emil B. Song ◽  
Sung Min Kim

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