scholarly journals Semiconductor Chip Electrical Interconnection and Bonding by Nano-Locking with Ultra-Fine Bond-Line Thickness

Nanomaterials ◽  
2021 ◽  
Vol 11 (8) ◽  
pp. 1901
Author(s):  
Jielin Guo ◽  
Yu-Chou Shih ◽  
Roozbeh Sheikhi ◽  
Jiun-Pyng You ◽  
Frank G. Shi

The potential of an innovation for establishing a simultaneous mechanical, thermal, and electrical connection between two metallic surfaces without requiring a prior time-consuming and expensive surface nanoscopic planarization and without requiring any intermediate conductive material has been explored. The method takes advantage of the intrinsic nanoscopic surface roughness on the interconnecting surfaces: the two surfaces are locked together for electrical interconnection and bonding with a conventional die bonder, and the connection is stabilized by a dielectric adhesive filled into nanoscale valleys on the interconnecting surfaces. This “nano-locking” (NL) method for chip interconnection and bonding is demonstrated by its application for the attachment of high-power GaN-based semiconductor dies to its device substrate. The bond-line thickness of the present NL method achieved is under 100 nm and several hundred times thinner than those achieved using mainstream bonding methods, resulting in a lower overall device thermal resistance and reduced electrical resistance, and thus an improved overall device performance and reliability. Different bond-line thickness strongly influences the overall contact area between the bonding surfaces, and in turn results in different contact resistance of the packaged devices enabled by the NL method and therefore changes the device performance and reliability. The present work opens a new direction for scalable, reliable, and simple nanoscale off-chip electrical interconnection and bonding for nano- and micro-electrical devices. Besides, the present method applies to the bonding of any surfaces with intrinsic or engineered surface nanoscopic structures as well.

Nanomaterials ◽  
2021 ◽  
Vol 11 (6) ◽  
pp. 1589
Author(s):  
Jielin Guo ◽  
Yu-Chou Shih ◽  
Frank G. Shi

The growing demand for increased chip performance and stable reliability calls for the development of novel off-chip interconnection and bonding methods that can process good electrical, thermal, and mechanical performance simultaneously as well as superior reliability. A chip bonding method with the concept of “nano-locking” (NL) is proposed: the two surfaces are locked together for electrical interconnection, and the connection is stabilized by a dielectric adhesive filled into nanoscale valleys on the interconnecting surfaces. The general applicability of this new method was investigated by applying the method to the die-substrate bonding of two different packages from two different manufacturers. Electrical, optical, and thermal performances as well as reliability tests were carried out. The surface morphology of the bonding package substrates plays an important role in determining the contact resistance at the bonding interfaces. It was shown that samples with different roughness height distribution on the metallic surfaces formed a different total number of contacts and the contact area between the two bonding surfaces under the same bond-line thickness (BLT): a larger number of contact area resulted in a reduced electrical resistance, and thus an improved overall device performance and reliability.


Materials ◽  
2021 ◽  
Vol 14 (7) ◽  
pp. 1723
Author(s):  
Yu Sekiguchi ◽  
Chiaki Sato

With an increasing demand for adhesives, the durability of joints has become highly important. The fatigue resistance of adhesives has been investigated mainly for epoxies, but in recent years many other resins have been adopted for structural adhesives. Therefore, understanding the fatigue characteristics of these resins is also important. In this study, the cyclic fatigue behavior of a two-part acrylic-based adhesive used for structural bonding was investigated using a fracture-mechanics approach. Fatigue tests for mode I loading were conducted under displacement control using double cantilever beam specimens with varying bond-line thicknesses. When the fatigue crack growth rate per cycle, da/dN, reached 10−5 mm/cycle, the fatigue toughness reduced to 1/10 of the critical fracture energy. In addition, significant changes in the characteristics of fatigue crack growth were observed varying the bond-line thickness and loading conditions. However, the predominance of the adhesive thickness on the fatigue crack growth resistance was confirmed regardless of the initial loading conditions. The thicker the adhesive bond line, the greater the fatigue toughness.


Author(s):  
E. Graycochea Jr. ◽  
F. Gomez ◽  
R. Rodriguez ◽  
B. Bacquian

Improvement on the process and design is often a reliable way to resolve a problem especially in semiconductor industry. This paper presents a leadframe or semiconductor carrier merged with a stand-off design structure that will maintain a consistent bond line thickness (BLT) criteria for quad-flat no-leads (QFN) packages. Through package and process conceptualization, the stand-off design located on the leadframe underneath the silicon die corners would result to a steady and consistent BLT during die attach process. With the improved design, die tilt occurrence in die attach process would be mitigated.


Author(s):  
Senthil A. G. Singaravelu ◽  
Xuejiao Hu ◽  
Kenneth E. Goodson

Increasing power dissipation in today’s microprocessors demands thermal interface materials (TIMs) with lower thermal resistances. The TIM thermal resistance depends on the TIM thermal conductivity and the bond line thickness (BLT). Carbon Nanotubes (CNTs) have been proposed to improve the TIM thermal conductivity. However, the rheological properties of TIMs with CNT inclusions are not well understood. In this paper, the transient behavior of the BLT of the TIMs with CNT inclusions has been measured under controlled attachment pressures. The experimental results show that the impact of CNT inclusions on the BLT at low volume fractions (up to 2 vol%) is small; however, higher volume fraction of CNT inclusions (5 vol%) can cause huge increase in TIM thickness. Although thermal conductivities are higher for higher CNT fractions, a minimum TIM resistance exists at some optimum CNT fraction for a given attachment pressure.


2009 ◽  
Vol 29 (7) ◽  
pp. 724-736 ◽  
Author(s):  
P. Davies ◽  
L. Sohier ◽  
J.-Y. Cognard ◽  
A. Bourmaud ◽  
D. Choqueuse ◽  
...  

2018 ◽  
Vol 109 ◽  
pp. 197-206 ◽  
Author(s):  
Francisco Sacchetti ◽  
Wouter J.B. Grouve ◽  
Laurent L. Warnet ◽  
Irene Fernandez Villegas

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