scholarly journals Improvement of Q rr-I DSS and dynamic avalanche of field-plate MOSFET by local lifetime control on the cathode side

2021 ◽  
Author(s):  
Yusuke Kobayashi ◽  
Tatsuya Nishiwaki ◽  
Akihiro Goryu ◽  
Tsuyoshi Kachi ◽  
Ryohei Gejo ◽  
...  
Keyword(s):  
Leakage Current ◽  
High Speed ◽  
Series Resistance ◽  
Device Simulation ◽  
Large Series ◽  
Cathode Side ◽  
Switching Loss ◽  
Trade Off ◽  
Field Plate ◽  
State Device

Abstract Reducing the reverse recovery charge (Qrr) is effective for reducing switching loss in field plate (FP)-MOSFETs. A lifetime killer is utilized to reduce Qrr while increasing the leakage current in the off-state. Device simulation shows that a local lifetime killer on the cathode side successfully improves the trade-off between Qrr and IDSS in comparison with that of a uniform lifetime killer. A known issue of cathode lifetime killers is overshoot voltage by hard recovery. However, the overshoot voltage of FP-MOSFET decreases with a cathode lifetime killer owing to an internal snubber, which is a feature of FP-MOSFETs. An internal snubber with a large series resistance causes dynamic avalanche by both the increase of FP potential and excess carriers in high-speed operation. The cathode lifetime killer also improves dynamic avalanche by excess carriers. Consequently, the cathode lifetime killer is preferable for high-speed FP-MOSFETs.

Development of high k/III-V (InGaAs, InAs, InSb) structures for future low power, high speed device applications

2013 ◽  
Vol 1538 ◽  
pp. 291-302
Author(s):  
Edward Yi Chang ◽  
Hai-Dang Trinh ◽  
Yueh-Chin Lin ◽  
Hiroshi Iwai ◽  
Yen-Ku Lin
Keyword(s):  
Low Power ◽  
Leakage Current ◽  
High Speed ◽  
High Performance ◽  
Gate Oxide ◽  
Chemical Cleaning ◽  
Low Leakage ◽  
Low Leakage Current ◽  
High K ◽  
Cleaning Methods

ABSTRACTIII-V compounds such as InGaAs, InAs, InSb have great potential for future low power high speed devices (such as MOSFETs, QWFETs, TFETs and NWFETs) application due to their high carrier mobility and drift velocity. The development of good quality high k gate oxide as well as high k/III-V interfaces is prerequisite to realize high performance working devices. Besides, the downscaling of the gate oxide into sub-nanometer while maintaining appropriate low gate leakage current is also needed. The lack of high quality III-V native oxides has obstructed the development of implementing III-V based devices on Si template. In this presentation, we will discuss our efforts to improve high k/III-V interfaces as well as high k oxide quality by using chemical cleaning methods including chemical solutions, precursors and high temperature gas treatments. The electrical properties of high k/InSb, InGaAs, InSb structures and their dependence on the thermal processes are also discussed. Finally, we will present the downscaling of the gate oxide into sub-nanometer scale while maintaining low leakage current and a good high k/III-V interface quality.

Large-size (1.7 × 1.7 mm2) β-Ga2O3 field-plated trench MOS-type Schottky barrier diodes with 1.2 kV breakdown voltage and 109 high on/off current ratio

2021 ◽  
Vol 15 (1) ◽  
pp. 016501
Author(s):  
Fumio Otsuka ◽  
Hironobu Miyamoto ◽  
Akio Takatsuka ◽  
Shinji Kunori ◽  
Kohei Sasaki ◽  
...  
Keyword(s):  
Schottky Barrier ◽  
Leakage Current ◽  
Schottky Barrier Diodes ◽  
Wafer Level ◽  
Current Ratio ◽  
Field Plate ◽  
Low Leakage ◽  
Large Size ◽  
Forward Current ◽  
Low Leakage Current

Abstract We fabricated high forward and low leakage current trench MOS-type Schottky barrier diodes (MOSSBDs) in combination with a field plate on a 12 μm thick epitaxial layer grown by halide vapor phase epitaxy on β-Ga2O3 (001) substrate. The MOSSBDs, measuring 1.7 × 1.7 mm2, exhibited a forward current of 2 A (70 A cm−2) at 2 V forward voltage and a leakage current of 5.7 × 10–10 A at −1.2 kV reverse voltage (on/off current ratio of > 109) with an ideality factor of 1.05 and wafer-level specific on-resistance of 17.1 mΩ · cm2.

Practical Aspects of Propulsion Shaft Alignment

2021 ◽  
Author(s):  
Kyriakos Avgouleas ◽  
Emmanouil Sarris ◽  
George Gougoulidis
Keyword(s):  
Cost Effectiveness ◽  
Numerical Model ◽  
High Speed ◽  
The Other ◽  
Technical Literature ◽  
Trade Off ◽  
Fea Model ◽  
Shaft Alignment ◽  
Alignment Strategy ◽  
Potential Damage

The economical and operational implications of poor alignment are indisputable for the propulsion shafting system of a commercial vessel. This holds true for naval vessels as well, although far less documented in the technical literature. This paper addresses some of the challenges associated with the proper alignment of a high-speed naval craft, which has been in service for many years. Laser bore-sighting was performed on a Guided Missile Fast Patrol Boat resting on a docking cradle. The measured bearing offsets were input to a FEA model of the shafting system to calculate bearing reactions and detect potential misalignment issues. Subsequent decisions regarding corrective measures take into account the results computed by the numerical model, experience from sister ships, the available documentation from the building yard and several other factors which are discussed in the paper. The solutions proposed are targeted towards a balanced trade-off between cost effectiveness and out-of-service time on one hand, and the risk of potential damage from misalignment on the other hand, which would seriously disrupt the ship’s operational availability. Practical aspects and lessons identified in the process are also presented, which demonstrate the distinct differences in alignment strategy of a high-speed naval craft compared to a typical commercial vessel.

Characterization of Low Temperature Polysilicon TFTs with Self-Aligned Graded LDD Structure

2001 ◽  
Vol 685 ◽  
Author(s):  
Ching-Wei Lin ◽  
Li-Jing Cheng ◽  
Yin-Lung Lu ◽  
Huang-Chung Cheng
Keyword(s):  
Low Temperature ◽  
Leakage Current ◽  
High Speed ◽  
High Reliability ◽  
Activation Process ◽  
Active Matrix ◽  
Dopant Activation ◽  
Low Leakage ◽  
Low Leakage Current ◽  
Excimer Laser Irradiation

AbstractA simple process sequence for fabrication of low temperature polysilicon (LTPS) TFTs with self-aligned graded LDD structure was demonstrated. The graded LDD structure was self-aligned by side-etch of Al under the photo-resist followed by excimer laser irradiation for dopant activation and laterally diffusion. The graded LDD polysilicon TFTs were suitable for high-speed operation and active matrix switches applications because they possessed low-leakage-current characteristic without sacrificing driving capability significantly and increasing overlap capacitance. The leakage current of graded LDD polysilicon TFTs at Vd = 5V and Vg = −10V could attain to below 1pA/μm without any hygrogenation process, when proper LDD length and laser activation process were applied. The on/off current ratios of these devices were also above 108. Furthermore, due to graded dopant distribution in LDD regions, the drain electric field could be reduced further, and as a result, graded LDD polysilicon TFTs provided high reliability for high voltage operation.

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