scholarly journals Link State Machine of PCI Express

2020 ◽  
Vol 9 (4) ◽  
pp. 1371-1372
Keyword(s):  
High Speed ◽  
Data Transfer ◽  
Physical Layer ◽  
State Machine ◽  
Data Link ◽  
Pci Express ◽  
Hard Drives ◽  
Link State ◽  
The Common ◽  
Communication Path

PCI Express is a high-speed serial computer expansion bus standard with advance error reporting technology. It is the common motherboard interface for personal computers' graphics cards, hard drives, SSDs, Wi-Fi and Ethernet hardware connections. A link in PCIe is the communication path between transmitter and receiver. PCIe operates in all transaction, data link and physical layer. The link bring up in physical layer is essential for the link state machine to proceed further into data transfer state. This paper analyses the Link training and status state machine for the Detect, Polling, Configuration and Recovery states. The state analysis is simulated using the TS1 and TS2 packets transfer between Root Complex and End Point.

Design of Data Transfer System Based on PCI Express Interface Applied in High-Speed Railway

2012 ◽  
Vol 229-231 ◽  
pp. 1543-1546
Author(s):  
Xiao Bo Zhou ◽  
Min Xia ◽  
Hai Long Cheng
Keyword(s):  
Data Acquisition ◽  
Data Transmission ◽  
High Speed ◽  
Data Transfer ◽  
Transmission Method ◽  
High Speed Railway ◽  
Pci Express ◽  
Data Acquisition Card ◽  
High Speed Data Acquisition ◽  
High Speed Data

To improve data transmission performance of the data acquisition card, a design of high-speed data transmission system is proposed in the thesis. Using FPGA of programmable logic devices, adopting Verilog HDL of hardware description language, the design of modularization and DMA transmission method is implemented in FPGA. Eventually the design implements the data transmission with high-speed through PCI Express interface. Through simulation and verification based on hardware system, this design is proved to be feasible and can satisfy the performance requirements of data transmission in the high-speed data acquisition card applied in high-speed railway communication. The design also has some value of application and reference for a universal data acquisition card.

The Design and Analysis on Communication Physical Layer of High-Speed Inter-Missile Networking

2011 ◽  
Vol 186 ◽  
pp. 332-336
Author(s):  
Yong Qi ◽  
Qian Mu Li ◽  
Xiang He Wei ◽  
Jie Yin
Keyword(s):  
Communication Network ◽  
Significant Role ◽  
High Speed ◽  
Physical Layer ◽  
Data Link ◽  
Control Center ◽  
Exchange Information ◽  
Single Data ◽  
And Control

Missile as a kind of weapon which plays a significant role in tactical strike, strategic strike and strategic deterrent, has been at the top position of the development of weapon in all country. This paper faces to the high-speed inter-missile networking, and design the deployment of the physical layer. All the missiles within the range of node running in the air automatically form a temporarily communication network, and any missile can communicate in the range of a node. When the distance between two missiles is more than the range of signal node, the message is relayed by neighbor nodes between them. Missiles can relay with satellite by configuring the satellite gateway, and send back to missile base and control center. The experiments show that the design in this paper improve the coverage of a single data link, which make the missiles efficient exchange information in network and lay a technique foundation for cooperation between missiles.

Protocol Conversion between PCI-Express and 1553B Bus

2012 ◽  
Vol 182-183 ◽  
pp. 501-505
Author(s):  
Peng An
Keyword(s):  
Data Transmission ◽  
System Integration ◽  
Tolerance Test ◽  
Physical Layer ◽  
Test Results ◽  
Data Link ◽  
Pci Express ◽  
Data Link Layer ◽  
Protocol Conversion ◽  
Fpga Chip

1553B bus is designed for aircraft developed an information transmission device bus standard, which is an agreement between devices. PCI Express is built on the PCI standard technology. It has the advantages of fast transmissions and strong reliability, so it can serve as a 1553B bus data transmission interface. The 1553B bus protocol includes data link layer, physical layer, and functional analysis. In the system, large scaled FPGA chip is used as the core. In its internal hardware, there are integrated PCI Express physical layer, while the PCI Express and 1553B bus protocol layer all in the internal FPGA implementation, carried out through the DMA the exchange of data in order to improve system integration. System testing includes f real-time, reliability and fault tolerance. Test results show that the whole system is well suitable for 1553B in the PCI Express environment applications.

scholarly journals Design and simulation of PCI Express physical layer

2015 ◽  
Vol 18 (3) ◽  
pp. 101-113
Author(s):  
Linh Thi Le Nguyen ◽  
Nhan Chi Nguyen ◽  
Dong An Bui ◽  
Hieu Van Nguyen
Keyword(s):  
Design Method ◽  
Physical Layer ◽  
System Level ◽  
Verilog Hdl ◽  
Data Link ◽  
Pci Express ◽  
Data Interchange ◽  
Analysis Design ◽  
Simulation Results ◽  
Link Data

This paper presents a detailed analysis, design and simulation of PCI Express Physical Layer. The Physical Layer isolates the Transaction and Data Link Layers from the signaling technology used for Link data interchange. The Physical Layer is divided into the logical and electrical subblocks. The paper designed Physical Layer in the system level with top-down design method and wrote the Verilog HDL codes to implement Physical Layer. Wrote testbench to verify the correctness of the design module for function simulation. The simulation results show that the designed Physical Layer meets the required of the function of PCI Express™ Physical layer Base Specification Revision 2.0.

scholarly journals Dual-shot dynamics and ultimate frequency of all-optical magnetic recording on GdFeCo

2021 ◽  
Vol 10 (1) ◽  
Author(s):  
Sicong Wang ◽  
Chen Wei ◽  
Yuanhua Feng ◽  
Hongkun Cao ◽  
Wenzhe Li ◽  
...  
Keyword(s):  
Magnetization Reversal ◽  
Energy Efficient ◽  
High Speed ◽  
Data Transfer ◽  
Laser Pulses ◽  
Time Resolved ◽  
All Optical ◽  
Fs Laser ◽  
High Speed Data ◽  
Natural Way

AbstractAlthough photonics presents the fastest and most energy-efficient method of data transfer, magnetism still offers the cheapest and most natural way to store data. The ultrafast and energy-efficient optical control of magnetism is presently a missing technological link that prevents us from reaching the next evolution in information processing. The discovery of all-optical magnetization reversal in GdFeCo with the help of 100 fs laser pulses has further aroused intense interest in this compelling problem. Although the applicability of this approach to high-speed data processing depends vitally on the maximum repetition rate of the switching, the latter remains virtually unknown. Here we experimentally unveil the ultimate frequency of repetitive all-optical magnetization reversal through time-resolved studies of the dual-shot magnetization dynamics in Gd27Fe63.87Co9.13. Varying the intensities of the shots and the shot-to-shot separation, we reveal the conditions for ultrafast writing and the fastest possible restoration of magnetic bits. It is shown that although magnetic writing launched by the first shot is completed after 100 ps, a reliable rewriting of the bit by the second shot requires separating the shots by at least 300 ps. Using two shots partially overlapping in space and minimally separated by 300 ps, we demonstrate an approach for GHz magnetic writing that can be scaled down to sizes below the diffraction limit.

Design and Implementation of a Multi-Channel HDLC Protocol Controller Based on FPGA

2011 ◽  
Vol 383-390 ◽  
pp. 6840-6845 ◽  
Author(s):  
Yong Hong Gu ◽  
Wei Huang ◽  
Qiao Li Yang
Keyword(s):  
Error Control ◽  
Data Transfer ◽  
Full Duplex ◽  
Programmable Logic ◽  
Data Link ◽  
Total Cost ◽  
Half Duplex ◽  
Level Data ◽  
Layer 2 ◽  
High Level

To transmit and receive data over any network successfully, a protocol is required to manage the flow. High-level Data Link Control (HDLC) protocol is defined in Layer 2 of OSI model and is one of the most commonly used Layer 2 protocol. HDLC supports both full-duplex and half-duplex data transfer. In addition, it offers error control and flow control. Currently on the market there are many dedicated HDLC chips, but these chips are neither of control complexity nor of limited number of channels. This paper presents a new method for implementing a multi-channel HDLC protocol controller using Altera FPGA and VHDL as the target technology. Implementing a multi-channel HDLC protocol controller in FPGA offers the flexibility, upgradability and customization benefits of programmable logic and also reduces the total cost of every project which involves HDLC protocol controllers.

scholarly journals Time-averaging of high-speed data transfer protocols

2005 ◽  
Vol 50 (12) ◽  
pp. 2065-2069 ◽  
Author(s):  
R. Marquez ◽  
E. Altman ◽  
S. Sole-Alvarez
Keyword(s):  
High Speed ◽  
Data Transfer ◽  
Time Averaging ◽  
High Speed Data

Optical Waveguides Embedded in PCBs - A Real World Application of 3D Structures Written by TPA

2007 ◽  
Vol 1054 ◽  
Author(s):  
Ruth Houbertz ◽  
Herbert Wolter ◽  
Volker Schmidt ◽  
Ladislav Kuna ◽  
Valentin Satzinger ◽  
...  
Keyword(s):  
Optical Fibers ◽  
Optical Waveguides ◽  
High Speed ◽  
Printed Circuit Boards ◽  
Data Transfer ◽  
Laser Pulses ◽  
Photon Absorption ◽  
Optical Data ◽  
Direct Laser ◽  
High Speed Data

ABSTRACTThe integration of optical interconnects in printed circuit boards (PCB) is a rapidly growing field worldwide due to a continuously increasing need for high-speed data transfer. There are any concepts discussed, among which are the integration of optical fibers or the generation of waveguides by UV lithography, embossing, or direct laser writing. The devices presented so far require many different materials and process steps, but particularly also highly-sophisticated assembly steps in order to couple the optoelectronic elements to the generated waveguides. In order to overcome these restrictions, an innovative approach is presented which allows the embedding of optoelectronic components and the generation of optical waveguides in only one optical material. This material is an inorganic-organic hybrid polymer, in which the waveguides are processed by two-photon absorption (TPA) processes, initiated by ultra-short laser pulses. In particular, due to this integration and the possibility ofin situpositioning the optical waveguides with respect to the optoelectronic components by the TPA process, no complex packaging or assembly is necessary. Thus, the number of necessary processing steps is significantly reduced, which also contributes to the saving of resources such as energy or solvents. The material properties and the underlying processes will be discussed with respect to optical data transfer in PCBs.

DCUDP: scalable data transfer for high-speed long-distance networks

2016 ◽  
Vol 29 (4) ◽  
pp. e3846
Author(s):  
Xu Zhang ◽  
Naijie Gu ◽  
Junjie Su
Keyword(s):  
High Speed ◽  
Data Transfer ◽  
Long Distance

Detecting Malicious Switches for a Secure Software-defined Tactile Internet

2021 ◽  
Vol 21 (4) ◽  
pp. 1-23
Author(s):  
Bin Yuan ◽  
Chen Lin ◽  
Deqing Zou ◽  
Laurence Tianruo Yang ◽  
Hai Jin
Keyword(s):  
High Speed ◽  
Data Transfer ◽  
Low Cost ◽  
Rapid Development ◽  
Denial Of Service ◽  
Linear Structure ◽  
Network Layers ◽  
High Speed Data ◽  
Network Status ◽  
Sdn Controller

The rapid development of the Internet of Things has led to demand for high-speed data transformation. Serving this purpose is the Tactile Internet, which facilitates data transfer in extra-low latency. In particular, a Tactile Internet based on software-defined networking (SDN) has been broadly deployed because of the proven benefits of SDN in flexible and programmable network management. However, the vulnerabilities of SDN also threaten the security of the Tactile Internet. Specifically, an SDN controller relies on the network status (provided by the underlying switches) to make network decisions, e.g., calculating a routing path to deliver data in the Tactile Internet. Hence, the attackers can compromise the switches to jeopardize the SDN and further attack Tactile Internet systems. For example, an attacker can compromise switches to launch distributed denial-of-service attacks to overwhelm the SDN controller, which will disrupt all the applications in the Tactile Internet. In pursuit of a more secure Tactile Internet, the problem of abnormal SDN switches in the Tactile Internet is analyzed in this article, including the cause of abnormal switches and their influences on different network layers. Then we propose an approach that leverages the messages sent by all switches to identify abnormal switches, which adopts a linear structure to store historical messages at a relatively low cost. By mapping each flow message to the flow establishment model, our method can effectively identify malicious SDN switches in the Tactile Internet and thus enhance its security.

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