scholarly journals Design of Area Efficent 32 Bit Arithmetic and Logic Unit (ALU) for DSP Processors

2019 ◽  
Vol 8 (6S3) ◽  
pp. 1270-1278
Keyword(s):  
Digital Signal Processor ◽  
High Performance ◽  
Design Procedure ◽  
Large Data ◽  
Digital Signal ◽  
Cmos Technology ◽  
Improved Performance ◽  
Dsp Processors ◽  
Low Complex ◽  
Bitwise Operations

Almost every electronic gadget contains the Digital signal processor (DSP) unit for the purpose of computations, whose role couldn’t be specified with smaller words. Gadget’s performance, efficiency and the importance could be measured with how best the specifications of the processors are. Arithmetic and Logical Unit (ALU) is the key circuit for any DSP processors, where large data computations can be performed. Hence, the ALUs design should be include high performance and large data handling capacity. An ALU is a digital electronic circuit that performs arithmetic and bitwise operations on integer binary numbers. The conventional ALU designs, design complexity rate proportionally increases with the performance demand. In this paper, an attempt has been given to design a low complex ALU with improved performance. Sub circuits designs comprise with new approaches to make the simple designs for higher performance of ALU. A 32 bit ALU design procedure has been demonstrated in this paper. For design, 90 nm CMOS technology and CADENCE virtuoso tools used.

scholarly journals SHIL and DHIL Simulations of Nonlinear Control Methods Applied for Power Converters Using Embedded Systems

Electronics ◽  
2018 ◽  
Vol 7 (10) ◽  
pp. 241 ◽  
Author(s):  
Arthur Rosa ◽  
Matheus Silva ◽  
Marcos Campos ◽  
Renato Santana ◽  
Welbert Rodrigues ◽  
...  
Keyword(s):  
Embedded Systems ◽  
Nonlinear Control ◽  
Real Time ◽  
Digital Signal Processor ◽  
High Performance ◽  
Power Converters ◽  
Digital Signal ◽  
Simulation Method ◽  
Hardware In The Loop ◽  
Control Techniques

In this work, a new real-time Simulation method is designed for nonlinear control techniques applied to power converters. We propose two different implementations: in the first one (Single Hardware in The Loop: SHIL), both model and control laws are inserted in the same Digital Signal Processor (DSP), and in the second approach (Double Hardware in The Loop: DHIL), the equations are loaded in different embedded systems. With this methodology, linear and nonlinear control techniques can be designed and compared in a quick and cheap real-time realization of the proposed systems, ideal for both students and engineers who are interested in learning and validating converters performance. The methodology can be applied to buck, boost, buck-boost, flyback, SEPIC and 3-phase AC-DC boost converters showing that the new and high performance embedded systems can evaluate distinct nonlinear controllers. The approach is done using matlab-simulink over commodity Texas Instruments Digital Signal Processors (TI-DSPs). The main purpose is to demonstrate the feasibility of proposed real-time implementations without using expensive HIL systems such as Opal-RT and Typhoon-HL.

scholarly journals Low Power Robust Early Output Asynchronous Block Carry Lookahead Adder with Redundant Carry Logic

Electronics ◽  
2018 ◽  
Vol 7 (10) ◽  
pp. 243 ◽  
Author(s):  
Padmanabhan Balasubramanian ◽  
Douglas Maskell ◽  
Nikos Mastorakis
Keyword(s):  
Low Power ◽  
Digital Signal Processor ◽  
Digital Signal ◽  
Complementary Metal Oxide Semiconductor ◽  
Low Power Design ◽  
Cmos Technology ◽  
General Purpose ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Power Cycle

Adder is an important datapath unit of a general-purpose microprocessor or a digital signal processor. In the nanoelectronics era, the design of an adder that is modular and which can withstand variations in process, voltage and temperature are of interest. In this context, this article presents a new robust early output asynchronous block carry lookahead adder (BCLA) with redundant carry logic (BCLARC) that has a reduced power-cycle time product (PCTP) and is a low power design. The proposed asynchronous BCLARC is implemented using the delay-insensitive dual-rail code and adheres to the 4-phase return-to-zero (RTZ) and the 4-phase return-to-one (RTO) handshaking. Many existing asynchronous ripple-carry adders (RCAs), carry lookahead adders (CLAs) and carry select adders (CSLAs) were implemented alongside to perform a comparison based on a 32/28 nm complementary metal-oxide-semiconductor (CMOS) technology. The 32-bit addition was considered for an example. For implementation using the delay-insensitive dual-rail code and subject to the 4-phase RTZ handshaking (4-phase RTO handshaking), the proposed BCLARC which is robust and of early output type achieves: (i) 8% (5.7%) reduction in PCTP compared to the optimum RCA, (ii) 14.9% (15.5%) reduction in PCTP compared to the optimum BCLARC, and (iii) 26% (25.5%) reduction in PCTP compared to the optimum CSLA.

PARALLEL ALGORITHMS FOR ADAPTIVE MATCHED-FIELD PROCESSING ON DISTRIBUTED ARRAY SYSTEMS

2004 ◽  
Vol 12 (02) ◽  
pp. 149-174 ◽  
Author(s):  
KILSEOK CHO ◽  
ALAN D. GEORGE ◽  
RAJ SUBRAMANIYAN ◽  
KEONWOOK KIM
Keyword(s):  
Parallel Algorithms ◽  
Real Time ◽  
Digital Signal Processor ◽  
High Performance ◽  
Digital Signal ◽  
Minimum Variance ◽  
Adaptive Beamforming ◽  
Matched Field Processing ◽  
Minimum Variance Distortionless Response ◽  
Distributed Array

Matched-field processing (MFP) localizes sources more accurately than plane-wave beamforming by employing full-wave acoustic propagation models for the cluttered ocean environment. The minimum variance distortionless response MFP (MVDR–MFP) algorithm incorporates the MVDR technique into the MFP algorithm to enhance beamforming performance. Such an adaptive MFP algorithm involves intensive computational and memory requirements due to its complex acoustic model and environmental adaptation. The real-time implementation of adaptive MFP algorithms for large surveillance areas presents a serious computational challenge where high-performance embedded computing and parallel processing may be required to meet real-time constraints. In this paper, three parallel algorithms based on domain decomposition techniques are presented for the MVDR–MFP algorithm on distributed array systems. The parallel performance factors in terms of execution times, communication times, parallel efficiencies, and memory capacities are examined on three potential distributed systems including two types of digital signal processor arrays and a cluster of personal computers. The performance results demonstrate that these parallel algorithms provide a feasible solution for real-time, scalable, and cost-effective adaptive beamforming on embedded, distributed array systems.

scholarly journals DSP-Based Control of Multi-Rail DC-DC Converter Systems with Non-Integer Switching Frequency Ratios

2011 ◽  
Vol 7 (1) ◽  
pp. 9-13
Author(s):  
James Mooney ◽  
Simon Effler ◽  
Mark Halton ◽  
Abdulhussain Mahdi
Keyword(s):  
Digital Signal Processor ◽  
Critical Factor ◽  
Digital Signal ◽  
Switching Frequency ◽  
Control Logic ◽  
Multiple Control ◽  
Analog To Digital ◽  
Improved Performance ◽  
The Individual ◽  
Frequency Ratios

This paper examines the use of non-integer switching frequency ratios in digitally controlled DC-DC converters. In particular the execution of multiple control algorithms using a Digital Signal Processor (DSP) for this application is analyzed. The variation in delay from when the Analog to Digital Converter (ADC) samples the output voltage to when the duty cycle is updated is identified as a critical factor to be considered when implementing the digital control system. Fixing the delay to its maximum value is found to produce reasonable performance using a conventional DSP. A modification of the DSP’s interrupt control logic is proposed here that minimizes the delay and thereby yields improved performance compared with that given by a standard interrupt controller. Applying this technique to a multi-rail power supply system provides the designer with the flexibility to choose arbitrary switching frequencies for individual converters, thereby allowing optimization of the efficiency and performance of the individual converters.

scholarly journals Optimizing Convolution Neural Network on the TI C6678 multicore DSP

2018 ◽  
Vol 246 ◽  
pp. 03044 ◽  
Author(s):  
Guozhao Zeng ◽  
Xiao Hu ◽  
Yueyue Chen
Keyword(s):  
Neural Network ◽  
Neural Networks ◽  
Image Processing ◽  
Deep Learning ◽  
Digital Signal Processor ◽  
High Performance ◽  
Digital Signal ◽  
Automatic Translation ◽  
Convolution Operation ◽  
Multicore Dsp

Convolutional Neural Networks (CNNs) have become the most advanced algorithms for deep learning. They are widely used in image processing, object detection and automatic translation. As the demand for CNNs continues to increase, the platforms on which they are deployed continue to expand. As an excellent low-power, high-performance, embedded solution, Digital Signal Processor (DSP) is used frequently in many key areas. This paper attempts to deploy the CNN to Texas Instruments (TI)’s TMS320C6678 multi-core DSP and optimize the main operations (convolution) to accommodate the DSP structure. The efficiency of the improved convolution operation has increased by tens of times.

Design of PMSM Position Servo System Based on Fuzzy Adaptive PI Control

2013 ◽  
Vol 706-708 ◽  
pp. 737-741 ◽  
Author(s):  
Hong Mei Shi ◽  
Zu Jun Yu
Keyword(s):  
Digital Signal Processor ◽  
High Performance ◽  
Permanent Magnet Synchronous Motor ◽  
Servo System ◽  
Experimental System ◽  
Digital Signal ◽  
Adaptive Controller ◽  
Speed Performance ◽  
Position Servo ◽  
Fuzzy Adaptive

A fuzzy adaptive PI controller for permanent magnet synchronous motor (PMSM) position servo system is proposed in this paper. Based on the analysis of PMSM mathematical model, the design of position loop controller is introduced in detail. To verify the effectiveness and accuracy of the fuzzy PI adaptive controller, an experimental system is designed using TMS320F2812 floating-point digital signal processor (DSP) as controller CPU and DR20A as integrated power drive module. The experimental results show that the designed AC position servo system has strong robustness, better speed performance and higher position precision, which can meet the requirements of high performance servo system.

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