scholarly journals DSP-Based Control of Multi-Rail DC-DC Converter Systems with Non-Integer Switching Frequency Ratios

2011 ◽  
Vol 7 (1) ◽  
pp. 9-13
Author(s):  
James Mooney ◽  
Simon Effler ◽  
Mark Halton ◽  
Abdulhussain Mahdi
Keyword(s):  
Digital Signal Processor ◽  
Critical Factor ◽  
Digital Signal ◽  
Switching Frequency ◽  
Control Logic ◽  
Multiple Control ◽  
Analog To Digital ◽  
Improved Performance ◽  
The Individual ◽  
Frequency Ratios

This paper examines the use of non-integer switching frequency ratios in digitally controlled DC-DC converters. In particular the execution of multiple control algorithms using a Digital Signal Processor (DSP) for this application is analyzed. The variation in delay from when the Analog to Digital Converter (ADC) samples the output voltage to when the duty cycle is updated is identified as a critical factor to be considered when implementing the digital control system. Fixing the delay to its maximum value is found to produce reasonable performance using a conventional DSP. A modification of the DSP’s interrupt control logic is proposed here that minimizes the delay and thereby yields improved performance compared with that given by a standard interrupt controller. Applying this technique to a multi-rail power supply system provides the designer with the flexibility to choose arbitrary switching frequencies for individual converters, thereby allowing optimization of the efficiency and performance of the individual converters.

scholarly journals DSP-Based Control of Multi-Rail DC-DC Converter Systems with Non-Integer Switching Frequency Ratios

2011 ◽  
Vol 7 (1) ◽  
pp. 9-13
Author(s):  
James Mooney ◽  
Simon Effler ◽  
Mark Halton ◽  
Abdulhussain Mahdi
Keyword(s):  
Digital Signal Processor ◽  
Critical Factor ◽  
Digital Signal ◽  
Switching Frequency ◽  
Control Logic ◽  
Multiple Control ◽  
Analog To Digital ◽  
Improved Performance ◽  
The Individual ◽  
Frequency Ratios

This paper examines the use of non-integer switching frequency ratios in digitally controlled DC-DC converters. In particular the execution of multiple control algorithms using a Digital Signal Processor (DSP) for this application is analyzed. The variation in delay from when the Analog to Digital Converter (ADC) samples the output voltage to when the duty cycle is updated is identified as a critical factor to be considered when implementing the digital control system. Fixing the delay to its maximum value is found to produce reasonable performance using a conventional DSP. A modification of the DSP’s interrupt control logic is proposed here that minimizes the delay and thereby yields improved performance compared with that given by a standard interrupt controller. Applying this technique to a multi-rail power supply system provides the designer with the flexibility to choose arbitrary switching frequencies for individual converters, thereby allowing optimization of the efficiency and performance of the individual converters.

Low Noise EEG Amplifier Board for Low Cost Wearable BCI Devices

2016 ◽  
Vol 5 (2) ◽  
pp. 17-28
Author(s):  
Ravim ◽  
Suma K. V.
Keyword(s):  
Noise Reduction ◽  
Digital Signal Processor ◽  
Low Cost ◽  
Processing System ◽  
Digital Signal ◽  
Low Noise ◽  
Digital Data ◽  
Signal Processing System ◽  
Analog To Digital ◽  
Reduction Techniques

Designing a real-time BCI device requires an Electroencephalogram (EEG) acquisition system and a signal processing system to process that acquired data. EEG acquisition boards available in market are expensive and they are required to be connected to computer for any processing work. Various low cost Digital Signal Processor (DSP) boards available in market come with internal Analog to Digital converters and peripheral interfaces. The idea is to design a low cost EEG amplifier board that can be used with these commercially available DSP boards. The analog data from EEG amplifier can be converted to digital data by DSP board and sent to computer via an interface for algorithm development and further control operations. EEG amplifiers are highly affected by noise from environment. Proper noise reduction techniques are implemented and simulated in circuit design. Each filter stage and noise reduction circuit is evaluated for a low noise design.

scholarly journals Design of Area Efficent 32 Bit Arithmetic and Logic Unit (ALU) for DSP Processors

2019 ◽  
Vol 8 (6S3) ◽  
pp. 1270-1278
Keyword(s):  
Digital Signal Processor ◽  
High Performance ◽  
Design Procedure ◽  
Large Data ◽  
Digital Signal ◽  
Cmos Technology ◽  
Improved Performance ◽  
Dsp Processors ◽  
Low Complex ◽  
Bitwise Operations

Almost every electronic gadget contains the Digital signal processor (DSP) unit for the purpose of computations, whose role couldn’t be specified with smaller words. Gadget’s performance, efficiency and the importance could be measured with how best the specifications of the processors are. Arithmetic and Logical Unit (ALU) is the key circuit for any DSP processors, where large data computations can be performed. Hence, the ALUs design should be include high performance and large data handling capacity. An ALU is a digital electronic circuit that performs arithmetic and bitwise operations on integer binary numbers. The conventional ALU designs, design complexity rate proportionally increases with the performance demand. In this paper, an attempt has been given to design a low complex ALU with improved performance. Sub circuits designs comprise with new approaches to make the simple designs for higher performance of ALU. A 32 bit ALU design procedure has been demonstrated in this paper. For design, 90 nm CMOS technology and CADENCE virtuoso tools used.

Recent Progress in Rapid-Single-Flux-Quantum Circuits

2006 ◽  
Vol 47 ◽  
pp. 180-187
Author(s):  
Akira Fujimaki ◽  
Takahiro Yamada ◽  
Masamitsu Tanaka ◽  
Hiroyuki Akaike ◽  
Nobuyuki Yoshikawa ◽  
...  
Keyword(s):  
Digital Signal Processor ◽  
Recent Progress ◽  
Digital Signal ◽  
Quantum Circuits ◽  
Flux Quantum ◽  
Analog To Digital ◽  
Rapid Single Flux Quantum ◽  
Line Technology ◽  
Multiple Detectors ◽  
Microprocessor Application

We describe recent topics of rapid-single-flux-quantum (RSFQ) circuits. Much higher integration and higher-speed operation are required for commercializing the RSFQ circuits in any application. To satisfy this requirement, we measure several kinds of time fluctuations that possibly limit the integration level and operating speed, and introduce the flexible passive transmission line technology including a multicasting transmitter. In addition, we describe our ongoing applications. A multiple-detectors-system is expected to open a new application field of an RSFQ-based analog-to-digital converter and a digital signal processor. As for a microprocessor application, increased number of arithmetic logic units may be effective for enhancing the computing performances.

Implementation on the FPGA of DTC-SVM Based Proportional Integral and Sliding Mode Controllers of an Induction Motor: A Comparative Study

2016 ◽  
Vol 26 (03) ◽  
pp. 1750049 ◽  
Author(s):  
Saber Krim ◽  
Soufien Gdaim ◽  
Abdellatif Mtibaa ◽  
Mohamed Faouzi Mimouni
Keyword(s):  
Induction Motor ◽  
Digital Signal Processor ◽  
Sliding Mode ◽  
Direct Torque Control ◽  
Digital Signal ◽  
Transient Behavior ◽  
Torque Control ◽  
Switching Frequency ◽  
Proportional Integral ◽  
Sliding Mode Controllers

The conventional direct torque control (DTC), based on the hysteresis controllers and the switching table, operates with a variable switching frequency, which decreases the conventional DTC performances, like the torque and flux ripples. Thus, the space vector modulation (SVM), used in the DTC, ensures a constant switching frequency and improves the DTC performances. The first aim of this paper is to present a comparison study between the DTC with an SVM (DTC-SVM) based on the Proportional Integral regulators (DTC-SVM-PI) and the DTC-SVM based on the sliding mode controllers (DTC-SVM-SMC). These two approaches are complex control algorithms which require faster micro-controllers; therefore the second objective of this paper is to present the implementation of the DTC-SVM-PI and the DTC-SVM-SMC on the Field Programmable Gate Array (FPGA), due to the parallel processing capability of the FPGAs. The two approaches are designed and simulated using the Xilinx System Generator (XSG) and implemented using an FPGA Virtex 5. The simulation results in the transient behavior and the steady state of the induction motor controlled by these two approaches are compared and discussed. The hardware FPGA implementation results show the effectiveness of the FPGA relative to the digital signal processor in terms of execution time.

Improving the Dynamic Response during Field Weakening Control of IPMSM Drive System using Adaptive Hysteresis Current Control Technique

2016 ◽  
Vol 17 (3) ◽  
pp. 235-249 ◽  
Author(s):  
Amiya Naik ◽  
Anup Kumar Panda ◽  
Sanjeeb Kumar Kar
Keyword(s):  
Digital Signal Processor ◽  
High Speed ◽  
Digital Signal ◽  
Torque Ripple ◽  
Current Control ◽  
Control Technique ◽  
Switching Frequency ◽  
Motor Speed ◽  
Current Controller ◽  
Current Error

Abstract This paper presents the control of IPMSM drive in flux weakening region, for high speed applications. An adaptive hysteresis band current controller has been designed and implemented in this work to overcome the drawbacks which are present in case of conventional hysteresis band current controllers such as: high torque ripple, more current error, large variation in switching frequency etc. The proposed current controller is a hysteresis controller in which the hysteresis band is programmed as a function of variation of motor speed and load current. Any variation in those parameters causes an appropriate change in the band which in turns reduces the torque ripple as well as current error of the machine. The proposed scheme is modeled and tested in the MATLAB-Simulink environment for the effectiveness of the study. Further, the result is validated experimentally by using TMS320F2812 digital signal processor.

scholarly journals Efficient FPSoC Prototyping of FCS-MPC for Three-Phase Voltage Source Inverters

Energies ◽  
2020 ◽  
Vol 13 (5) ◽  
pp. 1074 ◽  
Author(s):  
Eduardo Zafra ◽  
Sergio Vazquez ◽  
Hipolito Guzman Miranda ◽  
Juan A. Sanchez ◽  
Abraham Marquez ◽  
...  
Keyword(s):  
Digital Signal Processor ◽  
Computation Time ◽  
Digital Signal ◽  
Power Converter ◽  
Voltage Source ◽  
Switching Frequency ◽  
Digital Controllers ◽  
Voltage Source Inverters ◽  
High Switching Frequency ◽  
Three Phase

This work describes an efficient implementation in terms of computation time and resource usage in a Field-Programmable System-On-Chip (FPSoC) of a Finite Control Set Model Predictive Control (FCS-MPC) algorithm. As an example, the FCS-MPC implementation is used for the current reference tracking of a two-level three-phase power converter. The proposed solution is an enabler for using both complex control algorithms and digital controllers for high switching frequency semiconductor technologies. An original HW/SW (hardware and software) system architecture for an FPSoC is designed to take advantage of a modern operating system, while removing time uncertainty in real-time software tasks, and exploiting dedicated FPGA fabric for the most complex computations. In addition, two different architectures for the FPGA-implemented functionality are proposed and compared in order to study the area-speed trade-off. Experimental results show the feasibility of the proposed implementation, which achieves a speed hundreds of times faster than the conventional Digital Signal Processor (DSP)-based control platform.

scholarly journals On Field Weakening Performance of a Brushless Direct Current Motor with Higher Winding Inductance: Why Does Design Matter?

Energies ◽  
2018 ◽  
Vol 11 (11) ◽  
pp. 3119 ◽  
Author(s):  
Ozgur Ustun ◽  
Omer Kivanc ◽  
Seray Senol ◽  
Bekir Fincan
Keyword(s):  
Direct Current ◽  
Digital Signal Processor ◽  
Digital Signal ◽  
Speed Ratio ◽  
Bldc Motor ◽  
Performance Study ◽  
Element Analysis ◽  
Field Weakening ◽  
Fractional Slot Concentrated Winding ◽  
Improved Performance

This paper comprises the design, analysis, experimental verification and field weakening performance study of a brushless direct current (BLDC) motor for a light electric vehicle. The main objective is to design a BLDC motor having a higher value d-axis inductance, which implies an improved performance of field weakening and a higher constant power speed ratio (CPSR) operation. Field weakening operation of surface-mounted permanent magnet (SMPM) BLDC motors requires a large d-axis inductance, which is characteristically low for those motors due to large air gap and PM features. The design phases of the sub-fractional slot-concentrated winding structure with unequal tooth widths include the motivation and the computer aided study which is based on Finite Element Analysis using ANSYS Maxwell. A 24/20 slot–pole SMPM BLDC motor is chosen for prototyping. The designed motor is manufactured and performed at different phase-advanced currents in the field weakening region controlled by a TMS320F28335 digital signal processor. As a result of the experimental work, the feasibility and effectiveness of field weakening for BLDC motors are discussed thoroughly and the contribution of higher winding inductance is verified.

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