Optimized DA-reconfigurable FIR filters for software defined radio channelizer applications

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
C. Srinivasa Murthy ◽  
K. Sridevi
Keyword(s):  
Energy Efficiency ◽  
Power Dissipation ◽  
Software Defined Radio ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Software Tool ◽  
Building Blocks ◽  
Fir Filter ◽  
Content Type ◽  
Filter Length

Purpose In this paper, the authors present different methods for reconfigurable finite impulse response (RFIR) filter design. Distributed arithmetic (DA)-based reconfigurable FIR filter design is suitable for software-defined radio (SDR) applications. The main contribution of reconfiguration is reuse of registers, multipliers, adders and to optimize various parameters such as area, power dissipation, speed, throughput, latency and hardware utilizations of flip-flops and slices. Therefore, effective design of building blocks will be optimized for RFIR filter with all the above parameters. Design/methodology/approach The modified, direct form register structure of FIR filter contributes the reuse concept and allows utilization of less number of registers and parallel computation operations. The disadvantage of DA and other conventional methods is delay increases proportionally with filter length. This is due to different partial products generated by adders. The usage of adder and multipliers in DA-FIR filter restricts the area and power dissipation because of their complexity of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by parallel prefix adder (PPA) usage based on Ling equation. PPA uses shift-add multiplication, which is a repetitive process of addition, and this process is known as Bypass Zero feed multiplicand in direct multiplication, and the proposed technique optimizes area-power product efficiently. The modified DA (MDA)-based RFIR filter is designed for 64 taps filter length (N). The design is developed by using Verilog hardware description language and implemented on field-programmable gate array. Also, this design validates SDR channel equalizer. Findings Both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of XC7A100tCSG324 and exploited the advantages in area-delay, power-speed products and energy efficiency. The theoretical and practical comparisons have been carried out, and the results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed products and energy efficiency, which are improved by 14.5%, 23%, 6.5%, 34.2% and 21%, respectively. Originality/value The DA-based RFIR filter is validated using Chipscope Pro software tool on Artix-7 FPGA in Xilinx ISE design suite and compared constraint parameters with existing state-of-art results. It is also tested the filtering operation by applying the RFIR filter on Audio signals for removal of noisy signals and it is found that 95% of noise signals are filtered effectively.

Design and implementation of pervasive DA based FIR filter and feeder register based multiplier for software definedradio networks

2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Mohan Kumar ◽  
Ranga Raju
Keyword(s):  
Energy Efficiency ◽  
Impulse Response ◽  
Power Dissipation ◽  
Software Defined Radio ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Fir Filter ◽  
Infinite Impulse Response ◽  
Content Type ◽  
Field Programmable

Purpose Digital signal processing (DSP) applications such as finite impulse response (FIR) filter, infinite impulse response and wavelet transformation functions are mainly constructed using multipliers and adders. The performance of any digital applications is dependent on larger size multipliers, area and power dissipation. To optimize power and area, an efficient zero product and feeder register-based multiplier (ZP and FRBM) is proposed. Another challenging task in multipliers is summation of partial products (PP), results in more delay. To address this issue, the modified parallel prefix adder (PPA) is incorporated in multiplier design. In this work, different methods are studied and analyzed for designing FIR filter, optimized with respect to area, power dissipation, speed, throughput, latency and hardware utilization. Design/methodology/approach The distributed arithmetic (DA)-based reconfigurable FIR design is found to be suitable filter for software-defined radio (SDR) applications. The performance of adder and multipliers in DA-FIR filter restricts the area and power dissipation due to their complexity in terms of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by using PPA which is based on Ling equation. The MDA-RFIR filter is designed for higher filter length (N), i.e. N = 64 with 64 taps and this design is developed using Verilog hardware description language (HDL) and implemented on field-programmable gate array. The design is validated for SDR channel equalizer; both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of part name XC7A100tCSG324. Findings The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency. The theoretical and practical comparisons have been done, and the practically obtained results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed product and energy efficiency are better about 3.5 times, 31, 45 and 29%, respectively. Originality/value The MDA-RFIR for N = 64 is optimized about 33% in terms of area-delay, power-speed product and energy efficiency.

scholarly journals Design of 32 Tap Finite Impulse Response Filter using Vedic Multiplier and KoggeStone Adder

2019 ◽  
Vol 8 (2) ◽  
pp. 6138-6141
Keyword(s):  
Filter Design ◽  
Finite Impulse Response ◽  
Software Tool ◽  
Propagation Delay ◽  
Fir Filter ◽  
Filter Synthesis ◽  
Look Ahead ◽  
Vedic Multiplier ◽  
Ripple Carry Adder ◽  
Effective Performance

32 tap FIR Filter is designed utilizing Vedic multiplier and Kogge stone adder. Effective performance is important for FIR Filter design due to increasing complexity. Two basic opertaions of FIR Filter are multiplication and addition. So, for multiplication, vedic multiplier is used and addition is performed by KS adder which is faster than other adders like Ripple carry adder, Look ahead carry adder, Carry select adder etc. K S adder is used to overcome problem of carry propagation. The objective is to minimize the propagation delay i.e increasing the speed of filter. Synthesis & simulation is done by Xilinx ISE 14.7 software tool using VHDL.

Design and implementation of high-speed and low-power consumption Moore-based loopback adder on FPGA

2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
B.N. Mohan Kumar ◽  
H.G. Rangaraju
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Fir Filter ◽  
Analysis Tool ◽  
Content Type ◽  
Minimum Power ◽  
Minimum Power Consumption

PurposeFinite impulse response (FIR) digital filters are a general element in several digital signal processing (DSP) systems. In VLSI platform, FIR is a developing filter because the complexity of design grows with the length of the FIR filter and also it has less latency. Generally, the FIR filter is designed dominated by the multiplier and adder. The conventional FIR filters occupy more area because of several numbers of adders and multipliers for filter designs.Design/methodology/approachTo overcome this issue, the Vedic Multiplier (VM) and Moore-based LoopBack Adder (MLBA) approach-based optimal FIR filter were designed in this research. Normally, the coefficient has been generated manually, which performs the FIR filter operation. So, the coefficient was generated from the MATLAB filter design and analysis tool. All pass coefficient was introduced in this research, which performs the processing element (PE). The VM approach was utilized in the PE to multiply the filter inputs and coefficients. This research employs the Moore-based LBA (MLBA) in the accumulator for the adding output of the PE. An MLBA approach is a significantly reduced area and increases speed by applying a looping transform function. Here, the proposed method is called a VM-MLBA-FIR filter. In this research, the FIR filter was done in Field Programmable Gate Array (FPGA) Xilinx by using Verilog code on various Virtex devices.FindingsThe experiment results showed that VM-MLBA-FIR filter reduced 26.88% of device utilization and 0.32 W of minimum power consumption compared to the existing PSA-FIR filter.Originality/valueThe experiment results showed that VM-MLBA-FIR filter reduced 26.88% of device utilization and 0.32 W of minimum power consumption compared to the existing PSA-FIR filter.

Efficient VLSI architecture for FIR filter design using modified differential evolution ant colony optimization algorithm

Circuit World ◽  
2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Tintu Mary John ◽  
Shanty Chacko
Keyword(s):  
Differential Evolution ◽  
Frequency Domain ◽  
High Speed ◽  
Ant Colony Algorithm ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Fir Filter ◽  
Ant Colony ◽  
Fir Filters ◽  
Content Type

Purpose This paper aims to concentrate on an efficient finite impulse response (FIR) filter architecture in combination with the differential evolution ant colony algorithm (DE-ACO). For the design of FIR filter, the evolutionary algorithm (EA) is found to be very efficient because of its non-conventional, nonlinear, multi-modal and non-differentiable nature. While focusing with frequency domain specifications, most of the EA techniques described with the existing systems diverge from the power related matters. Design/methodology/approach The FIR filters are extensively used for many low power, low complexities, less area and high speed digital signal processing applications. In the existing systems, various FIR filters have been proposed to focus on the above criterion. Findings In the proposed method, a novel DE-ACO is used to design the FIR filter. It focuses on satisfying the economic power utilization and also the specifications in the frequency domain. Originality/value The proposed DE-ACO gives outstanding performance with a strong ability to find optimal solution, and it has got quick convergence speed. The proposed method also uses the Software integrated synthesis environment (ISE) project navigator (p.28xd) for the simulation of FIR filter based on DE-ACO techniques.

scholarly journals Constant-coefficient FIR filters based on residue number system arithmetic

2012 ◽  
Vol 9 (3) ◽  
pp. 325-342 ◽  
Author(s):  
Negovan Stamenkovic ◽  
Vladica Stojanovic
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
Finite Impulse Response ◽  
Number System ◽  
Residue Number System ◽  
Fir Filter ◽  
Fir Filters ◽  
Residue Number ◽  
Low Power Dissipation ◽  
Residue Arithmetic

In this paper, the design of a Finite Impulse Response (FIR) filter based on the residue number system (RNS) is presented. We chose to implement it in the (RNS), because the RNS offers high speed and low power dissipation. This architecture is based on the single RNS multiplier-accumulator (MAC) unit. The three moduli set {2n+1,2n,2n-1}, which avoids 2n+1 modulus, is used to design FIR filter. A numerical example illustrates the principles of residue encoding, residue arithmetic, and residue decoding for FIR filters.

Low Power Transposed Form 4-Tap Finite Impulse Response Filter using Power Efficient Multiply Accumulate Unit

2021 ◽  
pp. 2250016
Author(s):  
S. Rakesh ◽  
K. S. Vijula Grace
Keyword(s):  
Low Power ◽  
Impulse Response ◽  
Speech Processing ◽  
Video Processing ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Low Power Design ◽  
Fir Filter ◽  
Efficient Design ◽  
Power Efficient

Finite impulse response (FIR) filters find wide application in signal processing applications on account of the stability and linear phase response of the filter. These digital filters are used in applications, like biomedical engineering, wireless communication, image processing, speech processing, digital audio and video processing. Low power design of FIR filter is one of the major constraints that researchers are trying hard to achieve. This paper presents the implementation of a novel power efficient design of a 4-tap 16-bit FIR filter using a modified Vedic multiplier (MVM) and a modified Han Carlson adder (MHCA). The units are coded using Verilog hardware description language and simulated using Xilinx Vivado Design Suite 2015.2. The filter is synthesized for the 7-series Artix field programmable gate array with xc7a100tcsg324-1 as the target device. The proposed filter design showed an improvement of a maximum of 57.44% and a minimum of 2.44% in the power consumption compared to the existing models.

scholarly journals FIR Filter Design using Finfets at 22nm Technology

2019 ◽  
Vol 9 (2) ◽  
pp. 1292-1295
Keyword(s):  
Video Processing ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Digital Signal ◽  
Fir Filter ◽  
Fir Filters ◽  
Short Channel ◽  
Channel Effects ◽  
Complex Circuits ◽  
Fir Filter Design

Finite Impulse Response (FIR) filters are the most significantdevice in digital signal processing.In many Digital Signal Processing applications like wireless communication, image and video processing FIR filters are used.Digital FIR filters primarily consists of multipliers, adders and delay elements. Area, power optimization and speed are the key design metrics of FiniteImpulse Response filter.As more electronic devices are battery operated, power consumption constraint becomes a major issue. Multipliers are the core of FIR filters. They consume a lot of energy and are generally complex circuits. With each new process technologies, the short channel effects limit the performance of FIR filters at nano regime. Various architectures have been proposed to enhance the performance of FIR filter. In this paper, FIR filter is designed using FINFETs at 22nm technology using Hspice software.

A Fast On-Chip Adaptive Genetic Algorithm Processor for Evolutionary FIR Filter Implementation Using Hardware–Software Co-Design

2019 ◽  
Vol 29 (01) ◽  
pp. 2050014
Author(s):  
C. Ranjith ◽  
S. P. Joy Vasantha Rani
Keyword(s):  
Hardware Implementation ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Fir Filter ◽  
Adaptive Genetic Algorithm ◽  
Ip Core ◽  
Complete Evaluation ◽  
Flexible System ◽  
On Chip ◽  
The Impact

Recent studies show the impact of genetic algorithms (GA) in the design of evolutionary finite impulse response (FIR) filters. Studies have shown hardware and software method of GA implementation for design. Hardware method improves speed due to parallelism, pipelining and the absence of the function calls compared to software implementation. But area constraint was the main issue of hardware implementation. Therefore, this paper illustrates a hardware–software co-design concept to implement an Adaptive GA processor (AGAP) for FIR filter design. The architecture of AGAP uses adaptive crossover and mutation probabilities to speed up the convergence of the GA process. The AGAP architecture was implemented using Verilog Hardware Description Language (HDL) and instantiated as a custom intellectual property (IP) core to the soft-core MicroBlaze processor of Spartan 6 (XC6SLX45-3CSG324I) FPGA. The MicroBlaze processor controls the AGAP IP core and other interfaces using Embedded C programs. The experiment demonstrated a significant 134% improvement in speed over hardware implementation but with a marginal increase in area. The complete evaluation and evolution of the filter coefficients were executed on a single FPGA. The system on chip (SoC) concept enables a robust and flexible system.

Implementation of the Finite Impulse Response (FIR) Filter on the DSK TMS320C6713 Transceiver Using Windowing Techniques

2018 ◽  
Vol 6 (1) ◽  
pp. 1-8
Author(s):  
Adella Acqha Vico Addina
Keyword(s):  
Filter Design ◽  
Finite Impulse Response ◽  
Bandpass Filters ◽  
Fir Filter ◽  
Test Results ◽  
Rectangular Window ◽  
Filter Performance ◽  
Highpass Filter ◽  
Low Pass ◽  
High Pass

In this study, implementing the FIR filter with the Blackman window and Rectangular window methods with the types of low pass, highpass, and bandpass filters using 2 DSK TMS320C6713 boards as sender (Tx) and receiver (Rx) using the code composer studio (CCS) V software program. .3.1, which will then be displayed on Matlab to observe the output results. From the test results, data will be obtained which are then analyzed to determine the filter performance of the design results and the real implementation results using the DSK TMS320C6713. The results showed that the design of the low pass, high pass and bandpass filters was in accordance with the desired specifications, although in the highpass filter design, the filter results were still incomplete.

scholarly journals Design of a Low-Order FIR Filter for a High-Frequency Square-Wave Voltage Injection Method of the PMLSM Used in Maglev Train

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 729 ◽  
Author(s):  
He Zhao ◽  
Liwei Zhang ◽  
Jie Liu ◽  
Chao Zhang ◽  
Jiao Cai ◽  
...  
Keyword(s):  
High Frequency ◽  
Filter Design ◽  
Finite Impulse Response ◽  
Design Method ◽  
Fir Filter ◽  
Maglev Train ◽  
High Frequency Signal ◽  
Injection Method ◽  
High Frequency Response ◽  
Low Order

In position sensorless control based on a high-frequency pulsating voltage injection method, filters are used to complete the extraction of high-frequency response signals for position observation. A finite impulse response (FIR) filter has the advantages of good stability and linear phase. However, the FIR filter designed by using traditional methods has a high order which will cause a large time delay. This paper proposes a low-order FIR filter design method for a high-frequency signal injection method in the permanent magnet linear synchronous motor. Based on the frequency characteristics of the current signal, the requirement that the FIR filter needs to meet were analyzed. According to the amplitude–frequency characteristic of the FIR filter, these requirements were converted into constraint equations. By solving these equations, the coefficient of the FIR filter could be obtained. The simulation and experiment results showed the effectiveness of this low-order FIR filter.

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