scholarly journals Testing and Diagnosis of Delay Faults in Finfet VLSI Circuits using Non-Incremental Genetic Algorithm

2020 ◽  
Vol 9 (2) ◽  
pp. 1673-1679
Keyword(s):  
Genetic Algorithm ◽  
Critical Path ◽  
Research Work ◽  
Propagation Delay ◽  
Vlsi Circuits ◽  
Delay Faults ◽  
Path Delay ◽  
Noise Margin ◽  
Critical Path Delay ◽  
Margin Propagation

FinFet transistors are used in major semiconductor organizations which play a significant role in the development of the silicon industries. Due to few embedded memories and other circuit issues the transistors have specific faults in manufacturing, designing of the circuit etc. This paper presents an advanced test algorithm to diagnose those faults. The circuit with different gates is designed to identify the places having faults. In addition, algorithms such as non-incremental algorithms is used to find critical path, path delay and PDF of Critical path delay and Genetic Algorithm for optimisation of Critical path delay for sensitive test vector and no of iterations. The transfer characteristics curve is plotted along with the delay curve which helps in finding out the simulation parameters such as noise margin, propagation delay. The results in the methodology calculate the probability density function of the critical path by estimating mean, standard deviation and variance. The advantages of the integration of the two algorithms in this paper help in analyzing the specific faults in the circuits and the error correction of the broken link in the path analysis and has enhanced performance. Furthermore, more complicated circuits are analyzed for fault detection with different approach. In this paper the research work on testing, diagnosis, estimation of Critical path and PDF of Critical path delay faults for FinFET based Combinational Circuits for 20nm and 32 nm Technologies are presented for the first time using latest Non Incremental Genetic algorithm.

16x16-bit Binary Multiplier using High Speed Modified Compressor.

2020 ◽  
Vol 12 ◽  
Author(s):  
Subhashis Maitra
Keyword(s):  
Power Consumption ◽  
High Speed ◽  
Critical Path ◽  
Propagation Delay ◽  
Higher Order ◽  
Path Delay ◽  
Huge Number ◽  
Critical Path Delay ◽  
Binary Multiplier ◽  
Wallace Tree Multiplier

Background: For higher order multiplications, a huge number of adders or compressors are used to perform the addition of the partial products. Objective: Hence the area and the propagation delay will increase. Researchers are trying to reduce the numbers of additions of partial products. Method: In this paper, different modified compressor have been proposed and based on that compressors, 16x16-bit binary multiplier has been discussed. Results: The proposed design provide better area, power consumption, critical path delay and less number of transistor counts when compared to other design using the conventional compressors. Here the proposed method has been used in Wallace tree multiplier or Dadda tree multiplier. The compressor used here has been implemented using Microwind DSCH 3.8 lite. Conclusion: The modified compressor makes the multiplier faster and reduces the number of addition of partial products..

scholarly journals A design methodology for approximate multipliers in convolutional neural networks: A case of MNIST

2021 ◽  
Vol 10 (1) ◽  
pp. 1
Author(s):  
Kenta Shirane ◽  
Takahiro Yamamoto ◽  
Hiroyuki Tomiyama
Keyword(s):  
Neural Network ◽  
Neural Networks ◽  
Convolutional Neural Network ◽  
Design Methodology ◽  
Critical Path ◽  
High Accuracy ◽  
Path Delay ◽  
Trade Off ◽  
Critical Path Delay

In this paper, we present a case study on approximate multipliers for MNIST Convolutional Neural Network (CNN). We apply approximate multipliers with different bit-width to the convolution layer in MNIST CNN, evaluate the accuracy of MNIST classification, and analyze the trade-off between approximate multiplier’s area, critical path delay and the accuracy. Based on the results of the evaluation and analysis, we propose a design methodology for approximate multipliers. The approximate multipliers consist of some partial products, which are carefully selected according to the CNN input. With this methodology, we further reduce the area and the delay of the multipliers with keeping high accuracy of the MNIST classification.

scholarly journals Design of delay efficient Booth multiplier using pipelining

2018 ◽  
Vol 7 (2.16) ◽  
pp. 94
Author(s):  
Abhishek Choubey ◽  
SPV Subbarao ◽  
Shruti B. Choubey
Keyword(s):  
Critical Path ◽  
Arithmetic Operation ◽  
Vlsi Design ◽  
Digital Signal ◽  
Path Delay ◽  
Large Area ◽  
Booth Multiplier ◽  
Critical Path Delay ◽  
Long Latency ◽  
Comparison Results

Multiplication is one of the most an essential arithmetic operation used in numerous applications in digital signal processing and communications. These applications need transformations, convolutions and dot products that involve an enormous amount of multiplications of an operand with a constant. Typical examples include wavelet, digital filters, such as FIR or IIR. However, multiplier structures have relatively large area-delay product, long latency and significantly high power consumption compared to other the arithmetic structure. Therefore, low power multiplier design has been always a significant part of DSP structure for VLSI design. The Booth multiplier is promising as the most efficient amongst the others multiplier as it reduces the complexity of considerably than others. In this paper, we have proposed Booth-multiplier using seamless pipelining. Theoretical comparison results show that the proposed Booth multiplier requires less critical path delay compared to traditional Booth multiplier. ASIC simulation results show proposed radix-16 Booth multiplier 13% less critical path delay for word width n=16 and 17% less critical path delay compared for bit width n=32 to best existing radix-16 Booth multiplier. 

scholarly journals Approximate Array Multipliers

Electronics ◽  
2021 ◽  
Vol 10 (5) ◽  
pp. 630
Author(s):  
Padmanabhan Balasubramanian ◽  
Raunaq Nayar ◽  
Douglas L. Maskell
Keyword(s):  
Critical Path ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Total Power ◽  
Path Delay ◽  
Input And Output ◽  
Critical Path Delay ◽  
Standard Design ◽  
Array Multiplier ◽  
Array Multipliers

This article describes the design of approximate array multipliers by making vertical or horizontal cuts in an accurate array multiplier followed by different input and output assignments within the multiplier. We consider a digital image denoising application and show how different combinations of input and output assignments in an approximate array multiplier affect the quality of the denoised images. We consider the accurate array multiplier and several approximate array multipliers for synthesis. The multipliers were described in Verilog hardware description language and synthesized by Synopsys Design Compiler using a 32/28-nm complementary metal-oxide-semiconductor technology. The results show that compared to the accurate array multiplier, one of the proposed approximate array multipliers viz. PAAM01-V7 achieves a 28% reduction in critical path delay, 75.8% reduction in power, and 64.6% reduction in area while enabling the production of a denoised image that is comparable in quality to the image denoised using the accurate array multiplier. The standard design metrics such as critical path delay, total power dissipation, and area of the accurate and approximate multipliers are given, the error parameters of the approximate array multipliers are provided, and the original image, the noisy image, and the denoised images are also depicted for comparison.

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