DESIGN AND IMPLEMENTATION OF A HIGH SPEED CLOCK AND DATA RECOVERY DELAY LOCKED LOOP USING SC FILTER
2014 ◽
pp. 82-86
Keyword(s):
High Q
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This paper presents the design of a clock and data recovery circuit having a high data rate of 9.95328 Gb/s by using delay locked loop with Switched Capacitor (SC) filter to improve the jitter transfer function and jitter tolerance as it has high Q and low center frequency. From the results it is seen that the besides the conventional DLL circuit , the circuit using SC filter of fc= 311.04 MHz and Q=500 provides very low cut off frequency.
2020 ◽
Vol 9
(5)
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pp. 951-955
2009 ◽
Vol 44
(7)
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pp. 1914-1926
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2011 ◽
Vol 58
(7)
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pp. 422-426
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2002 ◽
Vol 40
(8)
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pp. 94-101
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Keyword(s):