scholarly journals Design of Low Power Amplifier for Brain Signal Measurement Applications

This paper presents the idea of analog amplifier which amplifies the amplitude of the real time EEG signals. This amplifier is for the front end application in brain signal measurement applications. In this paper instrumentation amplifier has been used for the designing purpose. The parameters of the proposed amplifier have been analyzed in order to achieve better gain and less power dissipation. The parameters like voltage, slew rate, gain bandwidth product, and sizing of Mosfet have been analyzed to achieve high gain using Cadence Virtuoso Software.

2020 ◽  
Vol 12 (3) ◽  
pp. 168-174
Author(s):  
Rashmi Sahu ◽  
Maitraiyee Konar ◽  
Sudip Kundu

Background: Sensing of biomedical signals is crucial for monitoring of various health conditions. These signals have a very low amplitude (in μV) and a small frequency range (<500 Hz). In the presence of various common-mode interferences, biomedical signals are difficult to detect. Instrumentation amplifiers (INAs) are usually preferred to detect these signals due to their high commonmode rejection ratio (CMRR). Gain accuracy and CMRR are two important parameters associated with any INA. This article, therefore, focuses on the improvement of the gain accuracy and CMRR of a low power INA topology. Objective: The objective of this article is to achieve high gain accuracy and CMRR of low power INA by having high gain operational amplifiers (Op-Amps), which are the building blocks of the INAs. Methods: For the implementation of the Op-Amps and the INAs, the Cadence Virtuoso tool was used. All the designs and implementation were realized in 0.18 μm CMOS technology. Results: Three different Op-Amp topologies namely single-stage differential Op-Amp, folded cascode Op-Amp, and multi-stage Op-Amp were implemented. Using these Op-Amp topologies separately, three Op-Amp-based INAs were realized and compared. The INA designed using the high gain multistage Op-Amp topology of low-frequency gain of 123.89 dB achieves a CMRR of 164.1 dB, with the INA’s gain accuracy as good as 99%, which is the best when compared to the other two INAs realized using the other two Op-Amp topologies implemented. Conclusion: Using very high gain Op-Amps as the building blocks of the INA improves the gain accuracy of the INA and enhances the CMRR of the INA. The three Op-Amp-based INA designed with the multi-stage Op-Amps shows state-of-the-art characteristics as its gain accuracy is 99% and CMRR is as high as 164.1 dB. The power consumed by this INA is 29.25 μW by operating on a power supply of ±0.9V. This makes this INA highly suitable for low power measurement applications.


1992 ◽  
Vol 28 (13) ◽  
pp. 1241 ◽  
Author(s):  
P. Wennekers ◽  
R. Bosch ◽  
W. Reinert ◽  
A. Huelsmann ◽  
G. Kaufel ◽  
...  

2015 ◽  
Vol 9 (2) ◽  
pp. 27-34 ◽  
Author(s):  
Shin-Gon Kim ◽  
Habib Rastegar ◽  
Min Yoon ◽  
Chul-Woo Park ◽  
Kyoungyong Park ◽  
...  

2021 ◽  
Vol 2021 ◽  
pp. 1-12
Author(s):  
Muhammad Ovais Akhter ◽  
Najam Muhammad Amin

This research proposed the design and calculations of ultra-low power (ULP) Doherty power amplifier (PA) using 65 nm CMOS technology. Both the main and the peaking amplifiers are designed and optimized using equivalent lumped parameters and power combiner models. The operation has been performed in RF-nMOS subthreshold or triode region to achieve ultra-low power (ULP) and to improve the linearity of the overall power amplifier (PA). The novel design consumes a DC power of 2.1 mW, power-added efficiency (PAE) of 29.8%, operating at 2.4 GHz band, and output referred 1 dB compression point at 4.1dBm. The simulation results show a very good capability of drive current, high gain, and very low input and output insertion losses.


2011 ◽  
Vol 147 ◽  
pp. 311-314
Author(s):  
Ming Yuan Ren ◽  
Chun Xiang Zhang ◽  
Jing Ying Zhao ◽  
Hai Guo

This paper presents a low-power multistage amplifier with a novel Transconductance with Capacitances Feedback Compensation (TCFC) technique. A transconductance stage and two capacitors introduce negative feedback to a three-stage amplifier, which significantly improves the performance such as gain-bandwidth product, slew rate, stability and sensitivity. Implemented in a commercial 0.5-μm CMOS technology and driving 10pF capacitive load, a three-stage TCFC amplifier achieves over 120dB gain, 1.515MHz GBW and 1.3V/μS average slew rate, while only dissipating 380μW under 3.3V supply.


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