Design and Simulation of Transconductance with Capacitances Feedback Compensation Amplifier

2011 ◽  
Vol 147 ◽  
pp. 311-314
Author(s):  
Ming Yuan Ren ◽  
Chun Xiang Zhang ◽  
Jing Ying Zhao ◽  
Hai Guo
Keyword(s):  
Low Power ◽  
Negative Feedback ◽  
Cmos Technology ◽  
Slew Rate ◽  
Gain Bandwidth ◽  
Feedback Compensation ◽  
Capacitive Load ◽  
Multistage Amplifier

This paper presents a low-power multistage amplifier with a novel Transconductance with Capacitances Feedback Compensation (TCFC) technique. A transconductance stage and two capacitors introduce negative feedback to a three-stage amplifier, which significantly improves the performance such as gain-bandwidth product, slew rate, stability and sensitivity. Implemented in a commercial 0.5-μm CMOS technology and driving 10pF capacitive load, a three-stage TCFC amplifier achieves over 120dB gain, 1.515MHz GBW and 1.3V/μS average slew rate, while only dissipating 380μW under 3.3V supply.

Design and Simulation of Low-Power Multistage Amplifiers

2011 ◽  
Vol 378-379 ◽  
pp. 655-658
Author(s):  
Ming Yuan Ren
Keyword(s):  
Low Power ◽  
Cmos Technology ◽  
Frequency Compensation ◽  
Transient Responses ◽  
Gain Bandwidth ◽  
Silicon Area ◽  
Multistage Amplifiers ◽  
Capacitive Load ◽  
The Stability ◽  
Multistage Amplifier

This paper presents a low-power multistage amplifier with a novel capacitor-multiplier frequency compensation (CMFC) technique. The proposed compensation strategy can allow the circuit to occupy less silicon area and to drive large capacitive loads more effectively. Moreover, smaller physical capacitance results in higher gain-bandwidth product (GBW) and improved transient responses. Furthermore, the capacitor multiplier stage (CMS) embedded in CMFC creates a left-half plane (LHP) zero, which boosts the phase margin and enhances the stability of the amplifier. Implemented in a commercial 0.5-μm CMOS technology and driving 500pF capacitive load, a three-stage CMFC amplifier achieves over 120dB gain, 1.699MHz GBW and 1.625V/μS average slew rate, while only dissipating 330μW under 3.3V supply.

scholarly journals A Modified Implementation of Tristate Inverter Based Static Master-Slave Flip-Flop with Improved Power-Delay-Area Product

2014 ◽  
Vol 2014 ◽  
pp. 1-14 ◽  
Author(s):  
Kunwar Singh ◽  
Satish Chandra Tiwari ◽  
Maneesha Gupta
Keyword(s):  
Low Power ◽  
Transient Response ◽  
High Performance ◽  
Cmos Technology ◽  
Flip Flop ◽  
Parasitic Extraction ◽  
Transmission Gate ◽  
Modern Process ◽  
Capacitive Load ◽  
Area Product

The paper introduces novel architectures for implementation of fully static master-slave flip-flops for low power, high performance, and high density. Based on the proposed structure, traditional C2MOS latch (tristate inverter/clocked inverter) based flip-flop is implemented with fewer transistors. The modified C2MOS based flip-flop designs mC2MOSff1 and mC2MOSff2 are realized using only sixteen transistors each while the number of clocked transistors is also reduced in case of mC2MOSff1. Postlayout simulations indicate that mC2MOSff1 flip-flop shows 12.4% improvement in PDAP (power-delay-area product) when compared with transmission gate flip-flop (TGFF) at 16X capacitive load which is considered to be the best design alternative among the conventional master-slave flip-flops. To validate the correct behaviour of the proposed design, an eight bit asynchronous counter is designed to layout level. LVS and parasitic extraction were carried out on Calibre, whereas layouts were implemented using IC station (Mentor Graphics). HSPICE simulations were used to characterize the transient response of the flip-flop designs in a 180 nm/1.8 V CMOS technology. Simulations were also performed at 130 nm, 90 nm, and 65 nm to reveal the scalability of both the designs at modern process nodes.

A LOW POWER CURRENT RECYCLING CONSTANT-gm RAIL-TO-RAIL OTA

2014 ◽  
Vol 23 (02) ◽  
pp. 1450022
Author(s):  
XIAO ZHAO ◽  
HUAJUN FANG ◽  
JUN XU
Keyword(s):  
Low Power ◽  
Bias Current ◽  
Cmos Process ◽  
Slew Rate ◽  
Gain Bandwidth ◽  
Design Specifications ◽  
Rail To Rail ◽  
Dc Gain ◽  
Unity Gain ◽  
Simulation Results

A low power current recycling constant-gm rail-to-rail (RtR) OTA is presented. The proposed amplifier has the benefit of delivering the same performance while consuming half the power compared to the conventional RtR amplifier. This is achieved by recycling the bias current of idle devices, which results in an enhanced transconductance, gain and slew rate. The proposed amplifier was implemented in CSMC standard 0.18 um CMOS process. Simulation results show that the proposed amplifier achieves 10.2 MHz unity-gain bandwidth, 59.4 dB DC gain, 4.8 V/us slew rate and less than 8% deviation in transconductance, but the power consumption reduced by 50% compared to the conventional RtR amplifier with the same design specifications.

scholarly journals A Low-Power Squaring Circuit with Regulated Output and Improved Settling Time in 180 nm CMOS for 3–5 GHz IR-UWB Applications

2021 ◽  
Vol 19 ◽  
pp. 79-84
Author(s):  
Daniel Schrüfer ◽  
Jürgen Röber ◽  
Timo Mai ◽  
Robert Weigel
Keyword(s):  
Transfer Function ◽  
Power Consumption ◽  
Low Power ◽  
Cmos Technology ◽  
Settling Time ◽  
Ultra Wideband ◽  
Quadratic Term ◽  
Slew Rate ◽  
Data Rates ◽  
5 Ghz

Abstract. This paper demonstrates a low-power squaring circuit for 3–5 GHz non-coherent Impulse-Radio Ultra-Wideband (IR-UWB) receivers for Pulse Position Modulation (PPM) in a low-cost 180 nm CMOS technology. The squaring, which is the key element in typical IR-UWB receivers, is performed exploiting the non-linear transfer function of a MOS transistor. For a high gain at low power consumption the transistor is biased in the moderate inversion region, where the second-order derivative of the transconductance gm and, as a result, the quadratic term in the transfer function reaches a maximum. A control loop was implemented to set the dc output voltage to a defined value and thus to allow a comparison of the squarer output signal with a defined threshold voltage, which can easily be set and adjusted (e.g. by a DAC). To speed up the settling time of the output and hence to reach higher data rates, a novel slew-rate booster is implemented at the output. Thereby, the squarer is capable of data rates of up to 15.6 Mbit s−1, which is more than two times higher compared to the circuit without the slew-rate booster, while only consuming 72.4 µW in addition. In the extracted post-layout simulations the whole circuitry consumes 724 µA at a 1.8 V power supply, resulting in a power consumption of 1.3 mW.

scholarly journals Design of Low Power Amplifier for Brain Signal Measurement Applications

2019 ◽  
Vol 8 (9) ◽  
pp. 686-688
Keyword(s):  
Low Power ◽  
Power Amplifier ◽  
Power Dissipation ◽  
High Gain ◽  
Instrumentation Amplifier ◽  
Slew Rate ◽  
Eeg Signals ◽  
Gain Bandwidth ◽  
Front End ◽  
Signal Measurement

This paper presents the idea of analog amplifier which amplifies the amplitude of the real time EEG signals. This amplifier is for the front end application in brain signal measurement applications. In this paper instrumentation amplifier has been used for the designing purpose. The parameters of the proposed amplifier have been analyzed in order to achieve better gain and less power dissipation. The parameters like voltage, slew rate, gain bandwidth product, and sizing of Mosfet have been analyzed to achieve high gain using Cadence Virtuoso Software.

Multistage Amplifier Using Dual-Miller with Nulling-Resistor and Dual-Feedforward Structure

2014 ◽  
Vol 989-994 ◽  
pp. 1169-1172
Author(s):  
Qian Neng Zhou ◽  
Qi Li ◽  
Jin Zhao Lin ◽  
Hong Juan Li ◽  
Chen Li ◽  
...  
Keyword(s):  
High Gain ◽  
Phase Margin ◽  
Slew Rate ◽  
Well Performance ◽  
Gain Bandwidth ◽  
Wide Bandwidth ◽  
Miller Compensation ◽  
Dc Gain ◽  
Simulation Results ◽  
Multistage Amplifier

This paper designs a high-gain wide-bandwidth multistage amplifier by employing the dual-miller compensation with nulling-resistor and dual-feedforward compensation (DMCNR-DFC) in 0.35μm BCD process. The designed DMCNR-DFC multistage amplifier achieves well performance including gain-bandwidth product (GBW) and slew rate (SR). Simulation results show that the DMCNR-DFC multistage amplifier achieves a dc gain of about 121.1dB and GBW of about 6.1MHz with 52o phase margin.

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