VLSI Design at the Undergraduate Level

This paper describes the experience gained in teaching a VLSI design course to students in the final year of a three-year course in Electronic Engineering. Each of the twenty students designed and tested their own full-custom CMOS integrated circuit within one academic year.

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Reading Process of Integrated Circuit Layout Debugging: Evidence from Eye Movements

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.787.855 ◽

2013 ◽

Vol 787 ◽

pp. 855-860

Author(s):

Hong Fa Ho

Keyword(s):

Eye Movements ◽

Integrated Circuit ◽

Region Of Interest ◽

Reading Process ◽

Ic Design ◽

Cmos Integrated Circuit ◽

Learning And Teaching ◽

Design Engineers ◽

Movement Data ◽

Electronic Engineering

Finding bugs in CMOS Integrated Circuit (IC) layouts is a basic skill for IC design engineers and students alike. The reading process of finding bugs is the basis for learning and teaching in electronic engineering. In this pilot study, eye-movement data was used in analyzing the reading process and nature of five participants (N=5) finding bugs in CMOS layouts. Data analysis of eye movements was based on nine types of ROI (Region of Interest). The ANOVA analysis of eye movements was analyzed. The findings of experimental results included that there were significant differences among the number of fixations of nine types of ROIs. The findings suggest how learners could read the bugged IC layouts effectively and efficiently.

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The Effects of Ionizing Radiation on Various CMOS Integrated Circuit Structures

IEEE Transactions on Nuclear Science ◽

10.1109/tns.1972.4326843 ◽

1972 ◽

Vol 19 (6) ◽

pp. 264-270 ◽

Cited By ~ 12

Author(s):

E. E. King ◽

G. P. Nelson ◽

H. L. Hughes

Keyword(s):

Ionizing Radiation ◽

Integrated Circuit ◽

Cmos Integrated Circuit

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Experimental Implementation of Networked Chaotic Oscillators Based on Cross-Coupled Inverter Rings in a CMOS Integrated Circuit

Journal of Circuits System and Computers ◽

10.1142/s0218126615501443 ◽

2015 ◽

Vol 24 (09) ◽

pp. 1550144 ◽

Cited By ~ 4

Author(s):

Ludovico Minati

Keyword(s):

Experimental Data ◽

Integrated Circuit ◽

Phase Synchronization ◽

Random Number Generation ◽

Partial Amplitude ◽

Chaotic Oscillator ◽

Chaotic Oscillators ◽

Cmos Integrated Circuit ◽

Experimental Implementation ◽

Small Clusters

A novel chaotic oscillator based on "cross-coupled" inverter rings is presented. The oscillator consists of a 3-ring to which higher odd n-rings are progressively coupled via diodes and pass gates; it does not contain reactive or resistive elements, and is thus suitable for area-efficient implementation on a CMOS integrated circuit. Numerical simulation based on piece-wise linear approximation predicted the generation of positive spikes having approximately constant periodicity but highly variable cycle amplitude. Simulation Program with Integrated Circuit Emphasis (SPICE) simulations and experimental data from a prototype realized on 0.7 μm technology confirmed this finding, and demonstrated increasing correlation dimension (D2) as 5-, 7- and 9-rings were progressively coupled to the 3-ring. Experimental data from a ring of 24 such oscillator cells showed phase synchronization and partial amplitude synchronization (formation of small clusters), emerging depending on DC gate voltage applied at NMOS transistors implementing diffusive coupling between neighboring cells. Thanks to its small area, simple synchronizability and digital controllability, the proposed circuit enables experimental investigation of dynamical complexity in large networks of coupled chaotic oscillators, and may additionally be suitable for applications such as broadband signal and random number generation.

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Pair Wise Swapping Based Hypergraph Partitioning Algorithms for VLSI Design

International Journal of Recent Technology and Engineering - 2 ◽

10.35940/ijrte.b3621.078219 ◽

2019 ◽

Vol 8 (2) ◽

pp. 5589-5593

Keyword(s):

Integrated Circuit ◽

Digital Camera ◽

Vlsi Design ◽

Electronic Systems ◽

Circuit Partitioning ◽

Computing Device ◽

Hypergraph Partitioning ◽

Vlsi Physical Design ◽

Portable Computing ◽

Partitioning Algorithms

A VLSI integrated circuit is the most significant part of electronic systems such as personal computer or workstation, digital camera, cell phone or a portable computing device, and automobile. So development within the field of electronic space depends on the design planning of VLSI integrated circuit. Circuit partitioning is most important step in VLSI physical design process. Many heuristic partitioning algorithms are proposed for this problem. The first heuristic algorithm for hypergraph partitioning in the domain of VLSI is FM algorithm. In this paper, I have proposed three variations of FM algorithm by utilizing pair insightful swapping strategies. I have played out a relative investigation of FM and my proposed algorithms utilizing two datasets for example ISPD98 and ISPD99. Test results demonstrate that my proposed calculations outflank the FM algorithm.

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A low-power CMOS integrated circuit for bearing estimation

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03. ◽

10.1109/iscas.2003.1206263 ◽

2003 ◽

Cited By ~ 11

Author(s):

P. Julian ◽

A. Andreou ◽

P. Mandolesi ◽

D. Goldberg

Keyword(s):

Low Power ◽

Integrated Circuit ◽

Cmos Integrated Circuit ◽

Bearing Estimation ◽

Low Power Cmos

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CMOS Circuits on Silicon Carbide for High Temperature Operation

MRS Proceedings ◽

10.1557/opl.2014.599 ◽

2014 ◽

Vol 1693 ◽

Cited By ~ 4

Author(s):

David T. Clark ◽

Robin F. Thompson ◽

Aled E. Murphy ◽

David A. Smith ◽

Ewan P. Ramsay ◽

...

Keyword(s):

Silicon Carbide ◽

High Temperature ◽

Wide Temperature Range ◽

Integrated Circuit ◽

Elevated Temperatures ◽

Logic Circuits ◽

Digital Logic ◽

Cmos Integrated Circuit ◽

Temperature Range ◽

Simple Logic

ABSTRACTWe present the characteristics of a high temperature CMOS integrated circuit process based on 4H silicon carbide designed to operate at temperatures beyond 300°C. N-channel and P-channel transistor characteristics at room and elevated temperatures are presented. Both channel types show the expected low values of field effect mobility well known in SiC MOSFETS. However the performance achieved is easily capable of exploitation in CMOS digital logic circuits and certain analogue circuits, over a wide temperature range.Data is also presented for the performance of digital logic demonstrator circuits, in particular a 4 to 1 analogue multiplexer and a configurable timer operating over a wide temperature range. Devices are packaged in high temperature ceramic dual in line (DIL) packages, which are capable of greater than 300°C operation. A high temperature “micro-oven” system has been designed and built to enable testing and stressing of units assembled in these package types. This system heats a group of devices together to temperatures of up to 300°C while keeping the electrical connections at much lower temperatures. In addition, long term reliability data for some structures such as contact chains to n-type and p-type SiC and simple logic circuits is summarized.

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PVT-Robust CMOS Programmable Chaotic Oscillator: Synchronization of Two 7-Scroll Attractors

Electronics ◽

10.3390/electronics7100252 ◽

2018 ◽

Vol 7 (10) ◽

pp. 252 ◽

Cited By ~ 11

Author(s):

Victor Carbajal-Gomez ◽

Esteban Tlelo-Cuautle ◽

Carlos Sanchez-Lopez ◽

Francisco Fernandez-Fernandez

Keyword(s):

Integrated Circuit ◽

Secure Communication ◽

Piecewise Linear ◽

Cmos Technology ◽

Oxide Semiconductor ◽

Chaotic Attractors ◽

Chaotic Oscillator ◽

Maximum Lyapunov Exponent ◽

Chaotic Oscillators ◽

Cmos Integrated Circuit

Designing chaotic oscillators using complementary metal-oxide-semiconductor (CMOS) integrated circuit technology for generating multi-scroll attractors has been a challenge. That way, we introduce a current-mode piecewise-linear (PWL) function based on CMOS cells that allow programmable generation of 2–7-scroll chaotic attractors. The mathematical model of the chaotic oscillator designed herein has four coefficients and a PWL function, which can be varied to provide a high value of the maximum Lyapunov exponent. The coefficients are implemented electronically by designing operational transconductance amplifiers that allow programmability of their transconductances. Design simulations of the chaotic oscillator are provided for the 0.35 μ m CMOS technology. Post-layout and process–voltage–temperature (PVT) variation simulations demonstrate robustness of the multi-scroll chaotic attractors. Finally, we highlight the synchronization of two seven-scroll attractors in a master–slave topology by generalized Hamiltonian forms and observer approach. Simulation results show that the synchronized CMOS chaotic oscillators are robust to PVT variations and are suitable for chaotic secure communication applications.

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