scholarly journals A High Performance Global Routing Algorithm on Julia Parallel Computing Platform

2021 ◽  
Vol 9 ◽  
pp. 103-108
Author(s):  
Meenakshi Agarwalla ◽  
Manash Pratim Sarma ◽  
Kandarpa Kumar Sarma
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Routing Algorithm ◽  
Global Routing ◽  
Careful Attention ◽  
Additional Advantage ◽  
C Language ◽  
Computing Platform ◽  
Sequential Processing ◽  
Design Requirements

o keep pace with the design requirements of Integrated Circuits (ICs), parallel processing is adopted. The path to be routed between two nodes may or may not be dependent on the previously routed paths. The solution requires careful attention in distributing the nets to be routed to different processors. Previous work on allocating the tasks to processors has been quite successful, reporting upto 3x improvement on 4 cores and 5x improvement on 8 core machine. The advantage of increasing the number of cores diminishes with each added processor and the challenge lies in being able to maintain the improvement per added core. The existing techniques of distributing the nets cannot provide additional advantage of using more than 8 cores. This paper improves the work on parallelizing global routing using a technique of balancing the load on the processors for better utilization of the resources. A relatively new budding platform Julia has been used which provides the ease of programming while maintaining the performance of the C language. Technique used in this paper has enabled to use 16 cores with routing solutions obtained in 0.8 minutes achieving 12.5 times speedup compared to sequential processing on a single core

A coupling and crosstalk-considered timing-driven global routing algorithm for high-performance circuit design

Integration ◽  
2006 ◽  
Vol 39 (4) ◽  
pp. 457-473 ◽  
Author(s):  
Jingyu Xu ◽  
Xianlong Hong ◽  
Tong Jing ◽  
Ling Zhang ◽  
Jun Gu
Keyword(s):  
Circuit Design ◽  
High Performance ◽  
Routing Algorithm ◽  
Global Routing

The Structure and Properties of MoSi2 Thin Film in Mos Process

1980 ◽  
Vol 38 ◽  
pp. 326-327
Author(s):  
C.K. Wu ◽  
P. Chang ◽  
N. Godinho
Keyword(s):  
Thin Film ◽  
Integrated Circuits ◽  
High Performance ◽  
Large Scale ◽  
Process Development ◽  
Structure And Properties ◽  
Metal Silicides ◽  
High Oxidation ◽  
Important Approach ◽  
High Oxidation Resistance

Recently, the use of refractory metal silicides as low resistivity, high temperature and high oxidation resistance gate materials in large scale integrated circuits (LSI) has become an important approach in advanced MOS process development (1). This research is a systematic study on the structure and properties of molybdenum silicide thin film and its applicability to high performance LSI fabrication.

A Working Method for Adapting the (SEM) Scanning Electron Microscope to Produce (STEM) Scanning Transmission Electron Microscope Images

2002 ◽  
Author(s):  
Edward Coyne
Keyword(s):  
Electron Microscope ◽  
High Resolution ◽  
Scanning Electron Microscope ◽  
Integrated Circuits ◽  
Theoretical Idea ◽  
Cross Sectional ◽  
Additional Advantage ◽  
Transmission Electron ◽  
Resolution Element ◽  
Scanning Electron

Abstract This paper describes the problems encountered and solutions found to the practical objective of developing an imaging technique that would produce a more detailed analysis of IC material structures then a scanning electron microscope. To find a solution to this objective the theoretical idea of converting a standard SEM to produce a STEM image was developed. This solution would enable high magnification, material contrasting, detailed cross sectional analysis of integrated circuits with an ordinary SEM. This would provide a practical and cost effective alternative to Transmission Electron Microscopy (TEM), where the higher TEM accelerating voltages would ultimately yield a more detailed cross sectional image. An additional advantage, developed subsequent to STEM imaging was the use of EDX analysis to perform high-resolution element identification of IC cross sections. High-resolution element identification when used in conjunction with high-resolution STEM images provides an analysis technique that exceeds the capabilities of conventional SEM imaging.

scholarly journals A Brief Overview of On-Chip Voltage Regulation in High-Performance and High-Density Integrated Circuits

IEEE Access ◽  
2021 ◽  
Vol 9 ◽  
pp. 813-826
Author(s):  
Farid Uddin Ahmed ◽  
Zarin Tasnim Sandhie ◽  
Liaquat Ali ◽  
Masud H. Chowdhury
Keyword(s):  
Integrated Circuits ◽  
High Performance ◽  
Voltage Regulation ◽  
High Density ◽  
On Chip

scholarly journals High-Performance On-Chip Silicon Beamsplitter Based on Subwavelength Metamaterials for Enhanced Fabrication Tolerance

Nanomaterials ◽  
2021 ◽  
Vol 11 (5) ◽  
pp. 1304
Author(s):  
Raquel Fernández de Cabo ◽  
David González-Andrade ◽  
Pavel Cheben ◽  
Aitor V. Velasco
Keyword(s):  
Integrated Circuits ◽  
Fundamental Mode ◽  
High Performance ◽  
Three Dimensional ◽  
High Sensitivity ◽  
Power Splitting ◽  
Excess Loss ◽  
Power Splitters ◽  
On Chip ◽  
Efficient Power

Efficient power splitting is a fundamental functionality in silicon photonic integrated circuits, but state-of-the-art power-division architectures are hampered by limited operational bandwidth, high sensitivity to fabrication errors or large footprints. In particular, traditional Y-junction power splitters suffer from fundamental mode losses due to limited fabrication resolution near the junction tip. In order to circumvent this limitation, we propose a new type of high-performance Y-junction power splitter that incorporates subwavelength metamaterials. Full three-dimensional simulations show a fundamental mode excess loss below 0.1 dB in an ultra-broad bandwidth of 300 nm (1400–1700 nm) when optimized for a fabrication resolution of 50 nm, and under 0.3 dB in a 350 nm extended bandwidth (1350–1700 nm) for a 100 nm resolution. Moreover, analysis of fabrication tolerances shows robust operation for the fundamental mode to etching errors up to ± 20 nm. A proof-of-concept device provides an initial validation of its operation principle, showing experimental excess losses lower than 0.2 dB in a 195 nm bandwidth for the best-case resolution scenario (i.e., 50 nm).

Polymeric aperture masks for high performance organic integrated circuits

2004 ◽  
Vol 22 (4) ◽  
pp. 1892-1895 ◽  
Author(s):  
Dawn V. Muyres ◽  
Paul F. Baude ◽  
Steven Theiss ◽  
Michael Haase ◽  
Tommie W. Kelley ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
High Performance
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