scholarly journals A CASE FOR HYBRID INSTRUCTION ENCODING FOR REDUCING CODE SIZE IN EMBEDDED SYSTEM-ON-CHIPS BASED ON RISC PROCESSOR CORES

2014 ◽  
Vol 10 (3) ◽  
pp. 411-422
Author(s):  
Bakthavatsalam
Keyword(s):  
Embedded System ◽  
Code Size ◽  
Hybrid Instruction ◽  
Risc Processor ◽  
Processor Cores

scholarly journals Improved Efficiency of Object Code Verification Using Statically Abstracted Object Code

2020 ◽  
Vol 2020 ◽  
pp. 1-19
Author(s):  
N. Shaukat ◽  
S. Shuja ◽  
S. K. Srinivasan ◽  
S. Jabeen
Keyword(s):  
Embedded System ◽  
Transition System ◽  
Object Code ◽  
Code Size ◽  
Large Size ◽  
Current State ◽  
The Common ◽  
The Embedded System ◽  
Verification Process ◽  
Manual Verification

One of the major challenges in the formal verification of embedded system software is the complexity and substantially large size of the implementation. The problem becomes crucial when the embedded system is a complex medical device that is executing convoluted algorithms. In refinement-based verification, both specification and implementation are expressed as transition systems. Each behavior of the implementation transition system is matched to the specification transition system with the help of a refinement map. The refinement map can only project those values from the implementation which are responsible for labeling the current state of the system. When the refinement map is applied at the object code level, numerous instructions map to a single state in the specification transition system called stuttering instructions. We use the concept of Static Stuttering Abstraction (SSA) that filters the common multiple segments of stuttering instructions and replaces each segment with a merger. SSA algorithm reduces the implementation state space in embedded software, subsequently decreasing the efforts involved in manual verification with WEB refinement. The algorithm is formally proven for correctness. SSA is implemented on the pacemaker object code to evaluate the effectiveness of abstracted code in verification process. The results helped to establish the fact that, despite code size reduction, the bugs and errors can still be found. We implemented the SSA technique on two different platforms and it has been proven to be consistent in decreasing the code size significantly and hence the complexity of the implementation transition system. The results illustrate that there is considerable reduction in time and effort required for the verification of a complex software control, i.e., pacemaker when statically stuttering abstracted code is employed.

scholarly journals On the correlation between testing effort and software complexity metrics

2018 ◽  
Author(s):  
Adnan Muslija ◽  
Eduard P Enoiu
Keyword(s):  
Embedded System ◽  
Execution Time ◽  
Test Cases ◽  
Code Size ◽  
Software Complexity ◽  
Test Execution ◽  
Complexity Metrics ◽  
Cyclomatic Complexity ◽  
Testing Effort ◽  
The Relationship

Software complexity metrics, such as code size and cyclomatic complexity, have been used in the software engineering community for predicting quality metrics such as maintainability, bug proneness and robustness. However, not many studies have addressed the relationship between complexity metrics and software testing and there is little experimental evidence to support the use of these code metrics in the estimation of test effort. We have investigated and evaluated the relationship between test effort (i.e, number of test cases and test execution time) and software complexity metrics for industrial control software used in an embedded system. We show how to measure different software complexity metrics such as number of elements, cyclomatic complexity, and information flow for a popular programming language named FBD used in the safety critical domain. In addition, we use test data and test suites created by experienced test engineers working at Bombardier Transportation Sweden AB to evaluate the correlation between several complexity measures and the testing effort. We found that there is a moderate correlation between software complexity metrics and test effort. In addition, the results show that the software size (i.e., number of elements in the FBD program) provides the highest correlation level with the number of test cases created and test execution time. Our results suggest that software size and structure metrics, while useful for identifying parts of the system that are more complicated, should not be solely used for identifying parts of the system for which test engineers might need to create more test cases. A potential explanation of this result concerns the nature of testing, since other attributes such as the level of thorough testing required and the size of the specifications can influence the creation of test cases. In addition, we used a linear regression model to estimate the test effort using the software complexity measurement results.

scholarly journals On the correlation between testing effort and software complexity metrics

2018 ◽  
Author(s):  
Adnan Muslija ◽  
Eduard P Enoiu
Keyword(s):  
Embedded System ◽  
Execution Time ◽  
Test Cases ◽  
Code Size ◽  
Software Complexity ◽  
Test Execution ◽  
Complexity Metrics ◽  
Cyclomatic Complexity ◽  
Testing Effort ◽  
The Relationship

Software complexity metrics, such as code size and cyclomatic complexity, have been used in the software engineering community for predicting quality metrics such as maintainability, bug proneness and robustness. However, not many studies have addressed the relationship between complexity metrics and software testing and there is little experimental evidence to support the use of these code metrics in the estimation of test effort. We have investigated and evaluated the relationship between test effort (i.e, number of test cases and test execution time) and software complexity metrics for industrial control software used in an embedded system. We show how to measure different software complexity metrics such as number of elements, cyclomatic complexity, and information flow for a popular programming language named FBD used in the safety critical domain. In addition, we use test data and test suites created by experienced test engineers working at Bombardier Transportation Sweden AB to evaluate the correlation between several complexity measures and the testing effort. We found that there is a moderate correlation between software complexity metrics and test effort. In addition, the results show that the software size (i.e., number of elements in the FBD program) provides the highest correlation level with the number of test cases created and test execution time. Our results suggest that software size and structure metrics, while useful for identifying parts of the system that are more complicated, should not be solely used for identifying parts of the system for which test engineers might need to create more test cases. A potential explanation of this result concerns the nature of testing, since other attributes such as the level of thorough testing required and the size of the specifications can influence the creation of test cases. In addition, we used a linear regression model to estimate the test effort using the software complexity measurement results.

Attendance Logging In Webserver Using Multi Node Embedded System Connected Through Wi-Fi

2012 ◽  
Vol 1 (3) ◽  
pp. 103
Author(s):  
Mohammed Bilal
Keyword(s):  
Embedded System ◽  
Web Pages ◽  
Web Based ◽  
Rfid Tag ◽  
Risc Processor ◽  
Machine Interface ◽  
The Embedded System ◽  
Distributed Measurement ◽  
And Control ◽  
Measurement And Control

In the present age, we are in need of fully automated attendance logging system. The design of Remote Attendance Logging System and its control is a challenging part.  RFID reader reads the RFID tag, and the details of the tag is logged in the embedded system. The Web based distributed measurement and control is slowly replacing parallel architectures due to its non-crate architecture which reduces complexities. A new kind  of expandable, distributed large attendance logging system based on ARM Cortex M3  boards has been investigated and developed in this paper, whose hardware boards use 32-bit RISC processor with wifi dongle attached to its USB port, and software platform use Keil MDK-ARM for firmware and   HTML for man machine interface.  This system can display date and time of log in and log out of a person. The data can be displayed on web pages at different geographical locations, and at the same time can be transmitted to a Remote Data Acquisition System by using HTTP protocol.  The embedded board can act as a central CPU to communicate between web servers automatically.

Low-cost software-based self-testing of RISC processor cores

2003 ◽  
Vol 150 (5) ◽  
pp. 355 ◽  
Author(s):  
N. Kranitis ◽  
G. Xenoulis ◽  
D. Gizopoulos ◽  
A. Paschalis ◽  
Y. Zorian
Keyword(s):  
Low Cost ◽  
Risc Processor ◽  
Self Testing ◽  
Processor Cores

CONVEYOR MODEL AND IMPLEMENTATION OF THE REAL NUMBERS ADDER ON FPGA

2020 ◽  
Vol 33 (109) ◽  
pp. 21-31
Author(s):  
І. Ya. Zeleneva ◽  
Т. V. Golub ◽  
T. S. Diachuk ◽  
А. Ye. Didenko
Keyword(s):  
Performance Improvement ◽  
Experimental Studies ◽  
Production Costs ◽  
Floating Point ◽  
Computing Device ◽  
Quartus Ii ◽  
Functional Blocks ◽  
Mental Testing ◽  
Processor Cores ◽  
Floating Point Numbers

The purpose of these studies is to develop an effective structure and internal functional blocks of a digital computing device – an adder, that performs addition and subtraction operations on floating- point numbers presented in IEEE Std 754TM-2008 format. To improve the characteristics of the adder, the circuit uses conveying, that is, division into levels, each of which performs a specific action on numbers. This allows you to perform addition / subtraction operations on several numbers at the same time, which increas- es the performance of calculations, and also makes the adder suitable for use in modern synchronous cir- cuits. Each block of the conveyor structure of the adder on FPGA is synthesized as a separate project of a digital functional unit, and thus, the overall task is divided into separate subtasks, which facilitates experi- mental testing and phased debugging of the entire device. Experimental studies were performed using EDA Quartus II. The developed circuit was modeled on FPGAs of the Stratix III and Cyclone III family. An ana- logue of the developed circuit was a functionally similar device from Altera. A comparative analysis is made and reasoned conclusions are drawn that the performance improvement is achieved due to the conveyor structure of the adder. Implementation of arithmetic over the floating-point numbers on programmable logic integrated cir- cuits, in particular on FPGA, has such advantages as flexibility of use and low production costs, and also provides the opportunity to solve problems for which there are no ready-made solutions in the form of stand- ard devices presented on the market. The developed adder has a wide scope, since most modern computing devices need to process floating-point numbers. The proposed conveyor model of the adder is quite simple to implement on the FPGA and can be an alternative to using built-in multipliers and processor cores in cases where the complex functionality of these devices is redundant for a specific task.

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