RESEARCH ON THE HIGH SPEED PERFORMANCE OF CHAIN-RING OVERRUNNING CLUTCH

2003 ◽  
Vol 39 (07) ◽  
pp. 116
Author(s):  
Jingyuan Huang
Author(s):  
Gaurav Mattey ◽  
Lava Ranganathan

Abstract Critical speed path analysis using Dynamic Laser Stimulation (DLS) technique has been an indispensable technology used in the Semiconductor IC industry for identifying process defects, design and layout issues that limit product speed performance. Primarily by injecting heat or injecting photocurrent in the active diffusion of the transistors, the laser either slows down or speeds up the switching speed of transistors, thereby affecting the overall speed performance of the chip and revealing the speed limiting/enhancing circuits. However, recently on Qualcomm Technologies’ 14nm FinFET technology SOC product, the 1340nm laser’s heating characteristic revealed a Vt (threshold voltage) improvement behavior at low operating voltages which helped identify process issues on multiple memory array blocks across multiple cores failing for MBIST (Memory Built-in Self-test). In this paper, we explore the innovative approach of using the laser to study Vt shifts in transistors due to process issues. We also study the laser silicon interactions through scanning the 1340nm thermal laser on silicon and observing frequency shifts in a high-speed Ring Oscillator (RO) on 16nm FinFET technology. This revealed the normal and reverse Temperature Dependency Gate voltages for 16nm FinFET, thereby illustrating the dual nature of stimulation (reducing mobility and improving Vt) from a thermal laser. Frequency mapping through Laser Voltage Imaging (LVI) was performed on the Ring Oscillator (RO) using the 1340nm thermal laser, while concurrently stimulating the transistors of the RO. Spatial distribution of stimulation was studied by observing the frequency changes on LVI.


2019 ◽  
Vol 13 (2) ◽  
pp. 174-180
Author(s):  
Poonam Sharma ◽  
Ashwani Kumar Dubey ◽  
Ayush Goyal

Background: With the growing demand of image processing and the use of Digital Signal Processors (DSP), the efficiency of the Multipliers and Accumulators has become a bottleneck to get through. We revised a few patents on an Application Specific Instruction Set Processor (ASIP), where the design considerations are proposed for application-specific computing in an efficient way to enhance the throughput. Objective: The study aims to develop and analyze a computationally efficient method to optimize the speed performance of MAC. Methods: The work presented here proposes the design of an Application Specific Instruction Set Processor, exploiting a Multiplier Accumulator integrated as the dedicated hardware. This MAC is optimized for high-speed performance and is the application-specific part of the processor; here it can be the DSP block of an image processor while a 16-bit Reduced Instruction Set Computer (RISC) processor core gives the flexibility to the design for any computing. The design was emulated on a Xilinx Field Programmable Gate Array (FPGA) and tested for various real-time computing. Results: The synthesis of the hardware logic on FPGA tools gave the operating frequencies of the legacy methods and the proposed method, the simulation of the logic verified the functionality. Conclusion: With the proposed method, a significant improvement of 16% increase in throughput has been observed for 256 steps iterations of multiplier and accumulators on an 8-bit sample data. Such an improvement can help in reducing the computation time in many digital signal processing applications where multiplication and addition are done iteratively.


2021 ◽  
Vol 1045 (1) ◽  
pp. 012040
Author(s):  
Fahim Faisal ◽  
Mirza Muntasir Nishat ◽  
Sayka Afreen Mim ◽  
Hafsa Akter ◽  
Md. Rafid Kaysar Shagor
Keyword(s):  

2003 ◽  
Vol 40 (01) ◽  
pp. 42-48
Author(s):  
Chang Doo Jang ◽  
Ho Kyung Kim ◽  
Ha Cheol Song

A surface effect ship is known to be comparable to a high-speed ship. For the structural design of surface effect ships, advanced design methods are needed which can reflect the various loading conditions different from those of conventional ships. Also, minimum weight design is essential because hull weight significantly affects the lift, thrust powering and high-speed performance. This paper presents the procedure of optimum structural design and a computer program to minimize the hull weight of surface effect ships built of composite materials. By using the developed computer program, the optimum structural designs for three types of surface effect ships—built of sandwich plate only, stiffened single skin plate only, and both plates—are carried out and the efficiency of each type is investigated in terms of weight. The computer program, developed herein, successfully reduced the hull weight of surface effect ships by 15–30% compared with the original design. Numerical results of optimum structural designs are presented and discussed.


Electronics ◽  
2018 ◽  
Vol 7 (12) ◽  
pp. 369 ◽  
Author(s):  
Padmanabhan Balasubramanian ◽  
Nikos Mastorakis

Addition is a fundamental operation in microprocessing and digital signal processing hardware, which is physically realized using an adder. The carry-lookahead adder (CLA) and the carry-select adder (CSLA) are two popular high-speed, low-power adder architectures. The speed performance of a CLA architecture can be improved by adopting a hybrid CLA architecture which employs a small-size ripple-carry adder (RCA) to replace a sub-CLA in the least significant bit positions. On the other hand, the power dissipation of a CSLA employing full adders and 2:1 multiplexers can be reduced by utilizing binary-to-excess-1 code (BEC) converters. In the literature, the designs of many CLAs and CSLAs were described separately. It would be useful to have a direct comparison of their performances based on the design metrics. Hence, we implemented homogeneous and hybrid CLAs, and CSLAs with and without the BEC converters by considering 32-bit accurate and approximate additions to facilitate a comparison. For the gate-level implementations, we considered a 32/28 nm complementary metal-oxide-semiconductor (CMOS) process targeting a typical-case process–voltage–temperature (PVT) specification. The results show that the hybrid CLA/RCA architecture is preferable among the CLA and CSLA architectures from the speed and power perspectives to perform accurate and approximate additions.


2015 ◽  
Vol 8 (3) ◽  
pp. 260-266
Author(s):  
Zhao Dong ◽  
Weiwei Zhang ◽  
He Qiang

VLSI Design ◽  
1998 ◽  
Vol 6 (1-4) ◽  
pp. 155-160
Author(s):  
A. M. Anile ◽  
O. Muscato ◽  
S. Rinaudo ◽  
P. Vergari

Recent advances in technology leads to increasing high speed performance of submicrometer electron devices by the scaling of both process and geometry. In order to aid the design of these devices it is necessary to utilize powerful numerical simulation tools. In an industrial environment the simulation codes based on the Drift-Diffusion models have been widely used. However the shrinking dimension of the devices causes the Drift-Diffusion based simulators to become less accurate. Then it is necessary to utilize more refined models (including higher order moments of the distribution function) in order to correctly predict the behaviour of these devices. Several hydrodynamical models have been considered as viable simulation tools. It is possible to discriminate among the several hydrodynamical models on the basis of their results on the output characteristics of the electron device which are measurable (I-V curves). We have analyzed two classes of hydrodynamical models: i) HFIELDS hydrodynamical models and HFIELDS drift-diffusion model; ii) self-consistent extended hydrodynamical models with relaxation times determined from Monte Carlo simulations.


2021 ◽  
Author(s):  
Siddharth Bhupendra Unadkat ◽  
Srikesh Kadakuntla ◽  
Venugopal Pandurangan ◽  
Aditya Pandey ◽  
S Ganesh ◽  
...  
Keyword(s):  

Sign in / Sign up

Export Citation Format

Share Document