scholarly journals Introduction to Stochastic Computing using a Remote Lab with Reconfigurable Logic

2016 ◽  
Vol 12 (04) ◽  
pp. 23
Author(s):  
Jorge Lobo

This short paper introduces the basic concepts of Stochastic Computing (SC), and presents additions to a remote lab with reconfigurable logic to allow testing SC circuits. Recently, SC has been revisited and evaluated as a possible way of performing approximate probabilistic computations for artificial perception systems. New modules allow the generation of pseudo-random numbers, given a seed key and using linear feedback shift registers, but also having true random number generation using ring oscillators and embedded PLLs. Stochastic computing allows a tradeoff between resource usage and precision, allowing very simple circuits to perform computations, at the expense of a longer integration time to have reasonable results. We provide the basic stochastic computing modules, so that any user can use them to build a stochastic computing circuit and go beyond software simulations, providing a remote hardware device to test real circuits at high clock speeds.

Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 195
Author(s):  
Hwasoo Shin ◽  
Soyeon Choi ◽  
Jiwoon Park ◽  
Byeong Yong Kong ◽  
Hoyoung Yoo

This paper presents a novel error detection linear feedback shift register (ED-LFSR), which can be used to realize error detection with a small hardware overhead for various applications such as error-correction codes, encryption algorithms and pseudo-random number generation. Although the traditional redundancy methods allow the incorporation of the error detection/correction capability in the original LFSRs, they suffer from a considerable amount of hardware overheads. The proposed ED-LFSR alleviates such problems by employing the parity check technique. The experimental results indicate that the proposed ED-LFSR requires an additional area of only 31.1% compared to that required by the conventional LFSR and it saves 39.1% and 31.9% of the resources compared to the corresponding utilization of the hardware and time redundancy methods.


Micromachines ◽  
2020 ◽  
Vol 12 (1) ◽  
pp. 31
Author(s):  
Junxiu Liu ◽  
Zhewei Liang ◽  
Yuling Luo ◽  
Lvchen Cao ◽  
Shunsheng Zhang ◽  
...  

Recent research showed that the chaotic maps are considered as alternative methods for generating pseudo-random numbers, and various approaches have been proposed for the corresponding hardware implementations. In this work, an efficient hardware pseudo-random number generator (PRNG) is proposed, where the one-dimensional logistic map is optimised by using the perturbation operation which effectively reduces the degradation of digital chaos. By employing stochastic computing, a hardware PRNG is designed with relatively low hardware utilisation. The proposed hardware PRNG is implemented by using a Field Programmable Gate Array device. Results show that the chaotic map achieves good security performance by using the perturbation operations and the generated pseudo-random numbers pass the TestU01 test and the NIST SP 800-22 test. Most importantly, it also saves 89% of hardware resources compared to conventional approaches.


2020 ◽  
Author(s):  
Gwangmin Kim ◽  
Jae Hyun In ◽  
Hakseung Rhee ◽  
Woojoon Park ◽  
Hanchan Song ◽  
...  

Abstract The intrinsic stochasticity of the memristor can be used to generate true random numbers, essential for non-decryptable hardware-based security devices. Here we propose a novel and advanced method to generate true random numbers utilizing the stochastic oscillation behavior of a NbOx mott memristor, exhibiting self-clocking, fast and variation tolerant characteristics. The random number generation rate of the device can be at least 40 kbs-1, which is the fastest record compared with previous volatile memristor-based TRNG devices. Also, its dimensionless operating principle provides high tolerance against both ambient temperature variation and device-to-device variation, enabling robust security hardware applicable in harsh environments.


Author(s):  
Padmapriya Praveenkumar ◽  
Santhiya Devi R. ◽  
Amirtharajan Rengarajan ◽  
John Bosco Balaguru Rayappan

Nano industries have been successful trendsetters for the past 30 years, in escalating the speed and dropping the power necessities of nanoelectronic devices. According to Moore's law and the assessment created by the international technology roadmap for semiconductors, beyond 2020, there will be considerable restrictions in manufacturing IC's based on CMOS technologies. As a result, the next prototype to get over these effects is quantum-dot cellular automata (QCA). In this chapter, an efficient quantum cellular automata (QCA) based random number generator (RNG) is proposed. QCA is an innovative technology in the nano regime which guarantees large device density, less power dissipation, and minimal size as compared to the various CMOS technologies. With the aim to maximise the randomness in the proposed nano communication, a linear feedback shift register (LFSR) keyed multiplexer with ring oscillators is developed. The developed RNG is simulated using a quantum cellular automata (QCA) simulator tool.


2018 ◽  
Vol 2018 ◽  
pp. 1-11 ◽  
Author(s):  
Seda Arslan Tuncer ◽  
Turgay Kaya

It is possible to generate personally identifiable random numbers to be used in some particular applications, such as authentication and key generation. This study presents the true random number generation from bioelectrical signals like EEG, EMG, and EOG and physical signals, such as blood volume pulse, GSR (Galvanic Skin Response), and respiration. The signals used in the random number generation were taken from BNCIHORIZON2020 databases. Random number generation was performed from fifteen different signals (four from EEG, EMG, and EOG and one from respiration, GSR, and blood volume pulse datasets). For this purpose, each signal was first normalized and then sampled. The sampling was achieved by using a nonperiodic and chaotic logistic map. Then, XOR postprocessing was applied to improve the statistical properties of the sampled numbers. NIST SP 800-22 was used to observe the statistical properties of the numbers obtained, the scale index was used to determine the degree of nonperiodicity, and the autocorrelation tests were used to monitor the 0-1 variation of numbers. The numbers produced from bioelectrical and physical signals were successful in all tests. As a result, it has been shown that it is possible to generate personally identifiable real random numbers from both bioelectrical and physical signals.


Sensors ◽  
2020 ◽  
Vol 20 (7) ◽  
pp. 1869 ◽  
Author(s):  
Luca Baldanzi ◽  
Luca Crocetti ◽  
Francesco Falaschi ◽  
Matteo Bertolucci ◽  
Jacopo Belli ◽  
...  

In the context of growing the adoption of advanced sensors and systems for active vehicle safety and driver assistance, an increasingly important issue is the security of the information exchanged between the different sub-systems of the vehicle. Random number generation is crucial in modern encryption and security applications as it is a critical task from the point of view of the robustness of the security chain. Random numbers are in fact used to generate the encryption keys to be used for ciphers. Consequently, any weakness in the key generation process can potentially leak information that can be used to breach even the strongest cipher. This paper presents the architecture of a high performance Random Number Generator (RNG) IP-core, in particular a Cryptographically Secure Pseudo-Random Number Generator (CSPRNG) IP-core, a digital hardware accelerator for random numbers generation which can be employed for cryptographically secure applications. The specifications used to develop the proposed project were derived from dedicated literature and standards. Subsequently, specific architecture optimizations were studied to achieve better timing performance and very high throughput values. The IP-core has been validated thanks to the official NIST Statistical Test Suite, in order to evaluate the degree of randomness of the numbers generated in output. Finally the CSPRNG IP-core has been characterized on relevant Field Programmable Gate Array (FPGA) and ASIC standard-cell technologies.


SPIN ◽  
2019 ◽  
Vol 10 (01) ◽  
pp. 2050003 ◽  
Author(s):  
Iman Alibeigi ◽  
Abdolah Amirany ◽  
Ramin Rajaei ◽  
Mahmoud Tabandeh ◽  
Saeed Bagheri Shouraki

Generation of random numbers is one of the most important steps in cryptographic algorithms. High endurance, high performance and low energy consumption are the attractive features offered by the Magnetic Tunnel Junction (MTJ) devices. Therefore, they have been considered as one of the promising candidates for next-generation digital integrated circuits. In this paper, a new circuit design for true random number generation using MTJs is proposed. Our proposed circuit offers a high speed, low power and a truly random number generation. In our design, we employed two MTJs that are configured in special states. Generated random bit at the output of the proposed circuit is returned to the write circuit to be written in the relevant cell for the next random generation. In a random bitstream, all bits must have the same chance of being “0”or “1”. We have proposed a new XOR-based method in this paper to resolve this issue in multiple random generators that produce truly random numbers with a different number of ones and zeros in the output stream. The simulation results using a 45[Formula: see text]nm CMOS technology with a special model of MTJ validated the advantages offered by the proposed circuit.


2019 ◽  
Vol 8 (3) ◽  
pp. 1854-1857

Random numbers are essential to generate secret keys, initialization vector, one-time pads, sequence number for packets in network and many other applications. Though there are many Pseudo Random Number Generators available they are not suitable for highly secure applications that require high quality randomness. This paper proposes a cryptographically secure pseudorandom number generator with its entropy source from sensor housed on mobile devices. The sensor data are processed in 3-step approach to generate random sequence which in turn fed to Advanced Encryption Standard algorithm as random key to generate cryptographically secure random numbers.


Author(s):  
A.F. Deon ◽  
V.A. Onuchin ◽  
Yu.A. Menyaev

Various pseudorandom number generation algorithms may be used to create a discrete stochastic plane. If a Cartesian completeness property is required of the plane, it must be uniform. The point is, employing the concept of uncontrolled random number generation may yield low-quality results, since original sequences may omit random numbers or not be sufficiently uniform. We present a novel approach for generating stochastic Cartesian planes according to the model of complete twister sequences featuring uniform random numbers without omissions or repetitions. Simulation results confirm that the random planes obtained are indeed perfectly uniform. Moreover, recombining the original complete uniform sequence parameters allows the number of planes created to be significantly increased without using any extra random access memory.


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