scholarly journals Area-Efficient Error Detection Structure for Linear Feedback Shift Registers

Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 195
Author(s):  
Hwasoo Shin ◽  
Soyeon Choi ◽  
Jiwoon Park ◽  
Byeong Yong Kong ◽  
Hoyoung Yoo

This paper presents a novel error detection linear feedback shift register (ED-LFSR), which can be used to realize error detection with a small hardware overhead for various applications such as error-correction codes, encryption algorithms and pseudo-random number generation. Although the traditional redundancy methods allow the incorporation of the error detection/correction capability in the original LFSRs, they suffer from a considerable amount of hardware overheads. The proposed ED-LFSR alleviates such problems by employing the parity check technique. The experimental results indicate that the proposed ED-LFSR requires an additional area of only 31.1% compared to that required by the conventional LFSR and it saves 39.1% and 31.9% of the resources compared to the corresponding utilization of the hardware and time redundancy methods.

2016 ◽  
Vol 12 (04) ◽  
pp. 23
Author(s):  
Jorge Lobo

This short paper introduces the basic concepts of Stochastic Computing (SC), and presents additions to a remote lab with reconfigurable logic to allow testing SC circuits. Recently, SC has been revisited and evaluated as a possible way of performing approximate probabilistic computations for artificial perception systems. New modules allow the generation of pseudo-random numbers, given a seed key and using linear feedback shift registers, but also having true random number generation using ring oscillators and embedded PLLs. Stochastic computing allows a tradeoff between resource usage and precision, allowing very simple circuits to perform computations, at the expense of a longer integration time to have reasonable results. We provide the basic stochastic computing modules, so that any user can use them to build a stochastic computing circuit and go beyond software simulations, providing a remote hardware device to test real circuits at high clock speeds.


Author(s):  
Padmapriya Praveenkumar ◽  
Santhiya Devi R. ◽  
Amirtharajan Rengarajan ◽  
John Bosco Balaguru Rayappan

Nano industries have been successful trendsetters for the past 30 years, in escalating the speed and dropping the power necessities of nanoelectronic devices. According to Moore's law and the assessment created by the international technology roadmap for semiconductors, beyond 2020, there will be considerable restrictions in manufacturing IC's based on CMOS technologies. As a result, the next prototype to get over these effects is quantum-dot cellular automata (QCA). In this chapter, an efficient quantum cellular automata (QCA) based random number generator (RNG) is proposed. QCA is an innovative technology in the nano regime which guarantees large device density, less power dissipation, and minimal size as compared to the various CMOS technologies. With the aim to maximise the randomness in the proposed nano communication, a linear feedback shift register (LFSR) keyed multiplexer with ring oscillators is developed. The developed RNG is simulated using a quantum cellular automata (QCA) simulator tool.


A ring oscillator based Random number generator (RNG) for Cryptography applications is presented. The paper explains about the requirements and generation of high randomness based codes, used to improve the security in data communication. The methodology used is sampling technique, adopted in the oscillator for the random number generation. To get better randomness in the output bits of RNG, a processor module based on Linear feedback shift register is used. The proposed RNG is designed with bit rate is 100kb/s, with a power consumption of 37µw. After implementation in hardware, this can be used for cryptography encryption applications to enhance the security. The system is simulated and synthesized with Xilinx ISE and the results are compared with the existing system based on randomness, power consumption, etc.


Nowadays security has become a great concern in the field of computer science and information technology. In order to protect data from unintended users and to achieve a desirable level of security, several cryptographic algorithms based on various technology have been proposed. Linear Feedback Shift Register (LFSR) may play an important role in the design of such cryptographic algorithms. LFSR based cryptographic algorithms are often lightweight in nature and are more suitable for resource constraining devices. In this paper we present a detailed analysis of LFSR and design of LFSR to implement cryptographic algorithms.


Author(s):  
Narendra Babu T ◽  
Fazal Noorbasha ◽  
Leenendra Chowdary Gunnam

In this article, an encryption algorithm with an error detection technique is presented for highly secured reliable data transmission over unreliable communication channels. In this algorithm, an input data is mapped into orthogonal code first. After that the code is encrypted with the help of Linear Feedback Shift Register (LFSR). The technique has been successfully verified and synthesized using Xilinx by Spartan-3E FPGA. The results show that the error detection rate has been increased to 100% by proposed encryption scheme is effective and improves bandwidth efficiency.


Author(s):  
Narendra Babu T ◽  
Fazal Noorbasha ◽  
Leenendra Chowdary Gunnam

In this article, an encryption algorithm with an error detection technique is presented for highly secured reliable data transmission over unreliable communication channels. In this algorithm, an input data is mapped into orthogonal code first. After that the code is encrypted with the help of Linear Feedback Shift Register (LFSR). The technique has been successfully verified and synthesized using Xilinx by Spartan-3E FPGA. The results show that the error detection rate has been increased to 100% by proposed encryption scheme is effective and improves bandwidth efficiency.


Sign in / Sign up

Export Citation Format

Share Document