8.3 kV 4H-SiC PiN Diode on (000-1) C-Face with Small Forward Voltage Degradation

2005 ◽  
pp. 969-972 ◽  
Author(s):  
Koji Nakayama ◽  
Yoshitaka Sugawara ◽  
Hidekazu Tsuchida ◽  
Toshiyuki Miyanagi ◽  
Isaho Kamata ◽  
...  
Keyword(s):  
Pin Diode ◽  
Forward Voltage ◽  
Voltage Degradation

Detecting Basal Plane Dislocations Converted in Highly Doped Epilayers

2019 ◽  
Vol 963 ◽  
pp. 272-275
Author(s):  
Yoshitaka Nishihara ◽  
Koji Kamei ◽  
Kenji Momose ◽  
Hiroshi Osawa
Keyword(s):  
Silicon Carbide ◽  
Basal Plane ◽  
Near Infrared ◽  
Minority Carrier ◽  
Pin Diode ◽  
Forward Voltage ◽  
Carrier Recombination ◽  
Near Ultraviolet ◽  
Bipolar Devices ◽  
Voltage Degradation

Suppression of the forward voltage degradation is essential in fabricating bipolar devices on silicon carbide. Using a highly N–doped 4H–epilayer as an enhancing minority carrier recombination layer is a powerful tool for reducing the expansion of BPDs converted at the epi/sub interface; however, these BPDs cannot be observed by using the near–infrared photoluminescence in the layer. Near–ultraviolet photoluminescence was instead used to detect BPDs as dark lines. In addition, a short BPD converted near the epi/sub interface and contributing to the degradation was detected. When this evaluation was applied to the fabrication of a pin diode including a highly N–doped 4H–epilayer, the Vf shift was suppressed in comparison with that in a diode without the layer.

Evaluation of Suppressing Forward Voltage Degradation by Using a Low BPD Density Substrate or an Epitaxial Wafer with an HNDE

2020 ◽  
Vol 1004 ◽  
pp. 439-444
Author(s):  
Yoshitaka Nishihara ◽  
Koji Kamei ◽  
Kenji Momose ◽  
Hiroshi Osawa
Keyword(s):  
Field Effect Transistor ◽  
Minority Carrier ◽  
Oxide Semiconductor ◽  
Pin Diode ◽  
Forward Voltage ◽  
Carrier Recombination ◽  
Crucial Problem ◽  
Basal Plane Dislocation ◽  
Effect Transistor ◽  
Voltage Degradation

Forward voltage degradation is a crucial problem that must be overcome if we are to fabricate a metal-oxide semiconductor field-effect transistor (MOSFET) including a pin diode (PND) as a body diode in a silicon carbide (SiC). Previously, the basal plane dislocation (BPD) in a SiC substrate have been reduced to suppress bipolar degradation. On the other hand, an highly N-doped epilayer (HNDE) was recently fabricated that enhances the minority carrier recombination before the carrier arrives at the substrate. Although both approaches can reduce the Vf shift caused by the degradation, they should be used under different substrate conditions. When a substrate with a high BPD density is used for epitaxial growth, an HNDE is needed to realize a high-quality epitaxial wafer; however, the HNDE should not be formed on a substrate with a low BPD density.

Dynamic Characteristics of 4H-SiC pin Diode on (000-1)C-Face with Small Forward Degradation

2006 ◽  
Vol 527-529 ◽  
pp. 1359-1362 ◽  
Author(s):  
Koji Nakayama ◽  
Yoshitaka Sugawara ◽  
R. Ishii ◽  
Hidekazu Tsuchida ◽  
Toshiyuki Miyanagi ◽  
...  
Keyword(s):  
Dynamic Characteristics ◽  
Stress Test ◽  
Pin Diode ◽  
Forward Voltage ◽  
Current Stress ◽  
Before And After ◽  
Voltage Degradation ◽  
A Current

Forward voltage degradation has been reduced by fabricating diodes on the (000-1)C-face. The reverse recovery characteristics of the 4H-SiC pin diode on the (000-1)C-face have been investigated. The pin diode on the C-face has superior potential to that on the Si-face among all parameters of the reverse recovery characteristics. The pin diode on the Si-face after conducting a current stress test tends to exhibit a fast turn-off as compared with that before conducting the stress test. On the C-face, however, there is little difference in reverse recovery characteristics between before and after conducting the current stress test.

Triangular Single Shockley Stacking Fault Analyses on 4H-SiC PiN Diode with Forward Voltage Degradation

2020 ◽  
Vol 49 (9) ◽  
pp. 5232-5239 ◽  
Author(s):  
Johji Nishio ◽  
Aoi Okada ◽  
Chiharu Ota ◽  
Mitsuhiro Kushibe
Keyword(s):  
Stacking Fault ◽  
Pin Diode ◽  
Forward Voltage ◽  
Voltage Degradation

8.3 kV 4H-SiC PiN Diode on (000-1) C-Face with Small Forward Voltage Degradation

2005 ◽  
Vol 483-485 ◽  
pp. 969-972 ◽  
Author(s):  
Koji Nakayama ◽  
Yoshitaka Sugawara ◽  
Hidekazu Tsuchida ◽  
Toshiyuki Miyanagi ◽  
Isaho Kamata ◽  
...  
Keyword(s):  
Breakdown Voltage ◽  
High Voltage ◽  
Pin Diode ◽  
Forward Voltage ◽  
Pin Diodes ◽  
High Breakdown Voltage ◽  
Voltage Degradation

The dependence of forward voltage degradation on crystal faces for 4H-SiC pin diodes has been investigated. The forward voltage degradation has been reduced by fabricating the diodes on the (000-1) C-face off-angled toward <11-20>. High-voltage 4H-SiC pin diodes on the (000-1) C-face with small forward voltage degradation have also been fabricated successfully. A high breakdown voltage of 4.6 kV and DVf of 0.04 V were achieved for a (000-1) C-face pin diode. A 8.3 kV blocking performance, which is the highest voltage in the use of (000-1) C-face, is also demonstrated in 4H-SiC pin diode.

Cause of Forward Voltage Degradation for 4H-SiC PiN Diode with Additional Process

2014 ◽  
Vol 1635 ◽  
pp. 121-126
Author(s):  
Tetsuro Hemmi ◽  
Koji Nakayama ◽  
Katsunori Asano ◽  
Tetsuya Miyazawa ◽  
Hidekazu Tsuchida
Keyword(s):  
Stress Test ◽  
Process Condition ◽  
Device Fabrication ◽  
Pin Diode ◽  
Forward Voltage ◽  
Pin Diodes ◽  
Half Loop ◽  
Additional Process ◽  
Voltage Degradation ◽  
A Current

ABSTRACTThe forward voltage degradation in 4H-SiC PiN diodes with a simplified process and that in 4H-SiC pin diodes with additional processes are investigated. Photoluminescence images were also observed to identify the cause of forward voltage degradation. The forward voltage degradations of 4H-SiC PiN diodes with additional processes were larger than those with a simplified process. Observing photoluminescence images of diodes after a current stress test showed that less than 25% of Shockley-type stacking faults in 4H-SiC PiN diodes with a simplified process are caused by half-loop dislocations, which are generated not only in the additional processes but also in the whole device fabrication process. With additional processes, those rates are over 65%, which may be reduced by eliminating half-loop dislocations due to the optimization of the process condition and sequence.

Modeling of Stacking Fault Expansion Velocity of Body Diode in 4H-SiC MOSFET

2017 ◽  
Vol 897 ◽  
pp. 214-217 ◽  
Author(s):  
Kumiko Konishi ◽  
Ryusei Fujita ◽  
Akio Shima ◽  
Yasuhiro Shimamoto
Keyword(s):  
Electrical Measurement ◽  
Stacking Fault ◽  
Junction Temperature ◽  
Expansion Velocity ◽  
Forward Voltage ◽  
Forward Current ◽  
Before And After ◽  
Voltage Degradation ◽  
Good Agreement

We present a model to explain forward voltage degradation of body diode in 4H-SiC MOSFET, and evaluate the velocity of SF expansion. First, by using in-situ photoluminescence (PL) observation, we investigated how a stacking fault (SF) expands from a basal plane dislocations (BPD) in the 4H-SiC epitaxial layer. Second, double-diffused MOSFETs were developed and measured before and after degradation. Then, the characteristics of the forward voltage degradation were modeled by a combination of PL imaging and electrical measurement, and the calculated characteristics are in good agreement with the measured ones. Finally, we tested the SiC MOSFETs under various stress conditions and evaluated the velocity of the SF expansion by calculation. This results indicate that the velocity of SF expansion increased with increasing forward current density and junction temperature.

High Current 6 kV 4H-SiC PiN Diodes for Power Module Switching Applications

2006 ◽  
Vol 527-529 ◽  
pp. 1355-1358 ◽  
Author(s):  
Brett A. Hull ◽  
Mrinal K. Das ◽  
Jim Richmond ◽  
Bradley Heath ◽  
Joseph J. Sumakeris ◽  
...  
Keyword(s):  
Pin Diode ◽  
High Current ◽  
Power Module ◽  
Temperature Dependent ◽  
Forward Voltage ◽  
Pin Diodes ◽  
Blocking Voltage ◽  
Chip Size ◽  
Switching Characteristics ◽  
Vf Drift

Forward voltage (VF) drift, in which a 4H-SiC PiN diode suffers from an irreversible increase in VF under forward current flow, continues to inhibit commercialization of 4H-SiC PiN diodes. We present our latest efforts at fabricating high blocking voltage (6 kV), high current (up to 50 A) 4H-SiC PiN diodes with the best combination of reverse leakage current (IR), forward voltage at rated current (VF), and VF drift yields. We have achieved greater than 60% total die yield onwafer for 50 A diodes with a chip size greater than 0.7 cm2. A comparison of the temperature dependent conduction and switching characteristics between a 50 A/6 kV 4H-SiC PiN diode and a commercially available 60 A/4.5 kV Si PiN diode is also presented.

Drift-Free, 50 A, 10 kV 4H-SiC PiN Diodes with Improved Device Yields

2005 ◽  
Vol 483-485 ◽  
pp. 965-968 ◽  
Author(s):  
Mrinal K. Das ◽  
Joseph J. Sumakeris ◽  
Brett A. Hull ◽  
Jim Richmond ◽  
Sumi Krishnaswami ◽  
...  
Keyword(s):  
Carrier Lifetime ◽  
Total Yield ◽  
Pin Diode ◽  
Forward Voltage ◽  
Reduction Processes ◽  
Dislocation Reduction ◽  
Good Crystalline Quality ◽  
Basal Plane Dislocation ◽  
High Carrier ◽  
High Degree

The path to commericializing a 4H-SiC power PiN diode has faced many difficult challenges. In this work, we report a 50 A, 10 kV 4H-SiC PiN diode technology where good crystalline quality and high carrier lifetime of the material has enabled a high yielding process with VF as low as 3.9 V @ 100 A/cm2. Furthermore, incorporation of two independent basal plane dislocation reduction processes (LBPD 1 and LBPD 2) have produced a large number of devices that exhibit a high degree of forward voltage stability with encouraging reverse blocking capability. This results in a total yield (forward, 10 kV blocking, and drift) of >20% for 8.7 mm x 8.7 mm power PiN diode chips—the largest SiC chip reported to date.

Investigation of Forward Voltage Degradation due to Process-Induced Defects in 4H-SiC MOSFET

2018 ◽  
Vol 924 ◽  
pp. 365-368 ◽  
Author(s):  
Kumiko Konishi ◽  
Ryusei Fujita ◽  
Yuki Mori ◽  
Akio Shima
Keyword(s):  
High Reliability ◽  
Stress Test ◽  
Implantation Dose ◽  
Imaging Method ◽  
Stress Tests ◽  
Forward Voltage ◽  
Current Stress ◽  
Before And After ◽  
Induced Defects ◽  
Voltage Degradation

We investigated process induced defects at various ion implantation conditions, and evaluated forward voltage degradation of body diode in 3.3 kV SiC MOSFET. First, by using photoluminescence (PL) observation, we evaluated the formation level of Basal Plane Dislocations (BPD) induced by Al implantation and anneal process with various Al implantation dose. Second, 3.3 kV double-diffused SiC MOSFETs were fabricated and forward current stress tests were performed to body diodes in SiC MOSFETs. Then, electrical characteristics of SiC MOSFETs before and after the stress test were measured, and expanded Stacking faults (SFs) in SiC epitaxial layer after the stress test were observed by PL imaging method. These results indicate that low dose or high temperature Al implantation conditions can suppress the formation of BPDs, and SiC MOSFETs fabricated using optimized Al implantation conditions show high reliability under current stress test.

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