Cause of Forward Voltage Degradation for 4H-SiC PiN Diode with Additional Process

ABSTRACTThe forward voltage degradation in 4H-SiC PiN diodes with a simplified process and that in 4H-SiC pin diodes with additional processes are investigated. Photoluminescence images were also observed to identify the cause of forward voltage degradation. The forward voltage degradations of 4H-SiC PiN diodes with additional processes were larger than those with a simplified process. Observing photoluminescence images of diodes after a current stress test showed that less than 25% of Shockley-type stacking faults in 4H-SiC PiN diodes with a simplified process are caused by half-loop dislocations, which are generated not only in the additional processes but also in the whole device fabrication process. With additional processes, those rates are over 65%, which may be reduced by eliminating half-loop dislocations due to the optimization of the process condition and sequence.

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Dynamic Characteristics of 4H-SiC pin Diode on (000-1)C-Face with Small Forward Degradation

Materials Science Forum ◽

10.4028/www.scientific.net/msf.527-529.1359 ◽

2006 ◽

Vol 527-529 ◽

pp. 1359-1362 ◽

Cited By ~ 2

Author(s):

Koji Nakayama ◽

Yoshitaka Sugawara ◽

R. Ishii ◽

Hidekazu Tsuchida ◽

Toshiyuki Miyanagi ◽

...

Keyword(s):

Dynamic Characteristics ◽

Stress Test ◽

Pin Diode ◽

Forward Voltage ◽

Current Stress ◽

Before And After ◽

Voltage Degradation ◽

A Current

Forward voltage degradation has been reduced by fabricating diodes on the (000-1)C-face. The reverse recovery characteristics of the 4H-SiC pin diode on the (000-1)C-face have been investigated. The pin diode on the C-face has superior potential to that on the Si-face among all parameters of the reverse recovery characteristics. The pin diode on the Si-face after conducting a current stress test tends to exhibit a fast turn-off as compared with that before conducting the stress test. On the C-face, however, there is little difference in reverse recovery characteristics between before and after conducting the current stress test.

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Effect of Stacking Faults Originating from Half Loop Arrays on Electrical Behavior of 10 kV 4H-SiC PiN Diodes

Materials Science Forum ◽

10.4028/www.scientific.net/msf.717-720.387 ◽

2012 ◽

Vol 717-720 ◽

pp. 387-390 ◽

Cited By ~ 10

Author(s):

Robert E. Stahlbush ◽

Qing Chun Jon Zhang ◽

Anant K. Agarwal ◽

Nadeemullah A. Mahadik

Keyword(s):

Basal Plane ◽

Forward Bias ◽

Stacking Faults ◽

Device Fabrication ◽

Electrical Behavior ◽

Forward Voltage ◽

Pin Diodes ◽

Electrical Stress ◽

Half Loop

The effects of Shockley stacking faults (SSFs) that originate from half loop arrays (HLAs) on the forward voltage and reverse leakage were measured in 10 kV 4H-SiC PiN diodes. The presence of HLAs and basal plane dislocations in each diode in a wafer was determined by ultraviolet photoluminescence imaging of the wafer before device fabrication. The SSFs were expanded by electrical stressing under forward bias of 30 A/cm2, and contracted by annealing at 550 °C. The electrical stress increased both the forward voltage and reverse leakage. Annealing returned the forward voltage and reverse leakage to nearly their original behavior. The details of SSF expansion and contraction from a HLA and the effects on the electrical behavior of the PiN diodes are discussed.

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Evolution of Drift-Free, High Power 4H-SiC PiN Diodes

Materials Science Forum ◽

10.4028/www.scientific.net/msf.527-529.1329 ◽

2006 ◽

Vol 527-529 ◽

pp. 1329-1334 ◽

Cited By ~ 5

Author(s):

Mrinal K. Das ◽

Joseph J. Sumakeris ◽

Brett A. Hull ◽

Jim Richmond

Keyword(s):

High Power ◽

Voltage Stability ◽

Fundamental Problem ◽

Minority Carrier Lifetime ◽

Device Fabrication ◽

Pin Diode ◽

Dramatic Improvement ◽

Forward Voltage ◽

Pin Diodes ◽

Fault Growth

The PiN diode is an attractive device to exploit the high power material advantages of 4H-SiC. The combination of high critical field and adequate minority carrier lifetime has enabled devices that block up to 20 kV and carry 25 A. Furthermore, these devices exhibit fast switching with less reverse recovery charge than commercially available Si PiN diodes. The path to commercialization of the 4H-SiC PiN diode technology, however, has been hampered by a fundamental problem with the forward voltage stability resulting from stacking fault growth emanating from basal plane screw dislocations (BPD). In this contribution, we highlight the progress toward producing stable high power devices with sufficient yield to promote commercial interest. Two independent processes, LBPD1 and LBPD2, have been shown to be effective in reducing the BPD density and enhancing the forward voltage stability while being compatible with conventional power device fabrication. Applying the LBPD1 and LBPD2 processes to 10 kV (20 A and 50 A) 4H-SiC PiN diode technology has resulted in a dramatic improvement in the total device yield (forward, reverse, and forward drift yields) from 0% to >20%. The LBPD1 process appears to be more robust in terms of long term forward voltage stability.

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8.3 kV 4H-SiC PiN Diode on (000-1) C-Face with Small Forward Voltage Degradation

Materials Science Forum ◽

10.4028/www.scientific.net/msf.483-485.969 ◽

2005 ◽

Vol 483-485 ◽

pp. 969-972 ◽

Cited By ~ 15

Author(s):

Koji Nakayama ◽

Yoshitaka Sugawara ◽

Hidekazu Tsuchida ◽

Toshiyuki Miyanagi ◽

Isaho Kamata ◽

...

Keyword(s):

Breakdown Voltage ◽

High Voltage ◽

Pin Diode ◽

Forward Voltage ◽

Pin Diodes ◽

High Breakdown Voltage ◽

Voltage Degradation

The dependence of forward voltage degradation on crystal faces for 4H-SiC pin diodes has been investigated. The forward voltage degradation has been reduced by fabricating the diodes on the (000-1) C-face off-angled toward <11-20>. High-voltage 4H-SiC pin diodes on the (000-1) C-face with small forward voltage degradation have also been fabricated successfully. A high breakdown voltage of 4.6 kV and DVf of 0.04 V were achieved for a (000-1) C-face pin diode. A 8.3 kV blocking performance, which is the highest voltage in the use of (000-1) C-face, is also demonstrated in 4H-SiC pin diode.

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Detecting Basal Plane Dislocations Converted in Highly Doped Epilayers

Materials Science Forum ◽

10.4028/www.scientific.net/msf.963.272 ◽

2019 ◽

Vol 963 ◽

pp. 272-275

Author(s):

Yoshitaka Nishihara ◽

Koji Kamei ◽

Kenji Momose ◽

Hiroshi Osawa

Keyword(s):

Silicon Carbide ◽

Basal Plane ◽

Near Infrared ◽

Minority Carrier ◽

Pin Diode ◽

Forward Voltage ◽

Carrier Recombination ◽

Near Ultraviolet ◽

Bipolar Devices ◽

Voltage Degradation

Suppression of the forward voltage degradation is essential in fabricating bipolar devices on silicon carbide. Using a highly N–doped 4H–epilayer as an enhancing minority carrier recombination layer is a powerful tool for reducing the expansion of BPDs converted at the epi/sub interface; however, these BPDs cannot be observed by using the near–infrared photoluminescence in the layer. Near–ultraviolet photoluminescence was instead used to detect BPDs as dark lines. In addition, a short BPD converted near the epi/sub interface and contributing to the degradation was detected. When this evaluation was applied to the fabrication of a pin diode including a highly N–doped 4H–epilayer, the Vf shift was suppressed in comparison with that in a diode without the layer.

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Evaluation of Suppressing Forward Voltage Degradation by Using a Low BPD Density Substrate or an Epitaxial Wafer with an HNDE

Materials Science Forum ◽

10.4028/www.scientific.net/msf.1004.439 ◽

2020 ◽

Vol 1004 ◽

pp. 439-444

Author(s):

Yoshitaka Nishihara ◽

Koji Kamei ◽

Kenji Momose ◽

Hiroshi Osawa

Keyword(s):

Field Effect Transistor ◽

Minority Carrier ◽

Oxide Semiconductor ◽

Pin Diode ◽

Forward Voltage ◽

Carrier Recombination ◽

Crucial Problem ◽

Basal Plane Dislocation ◽

Effect Transistor ◽

Voltage Degradation

Forward voltage degradation is a crucial problem that must be overcome if we are to fabricate a metal-oxide semiconductor field-effect transistor (MOSFET) including a pin diode (PND) as a body diode in a silicon carbide (SiC). Previously, the basal plane dislocation (BPD) in a SiC substrate have been reduced to suppress bipolar degradation. On the other hand, an highly N-doped epilayer (HNDE) was recently fabricated that enhances the minority carrier recombination before the carrier arrives at the substrate. Although both approaches can reduce the Vf shift caused by the degradation, they should be used under different substrate conditions. When a substrate with a high BPD density is used for epitaxial growth, an HNDE is needed to realize a high-quality epitaxial wafer; however, the HNDE should not be formed on a substrate with a low BPD density.

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High Current 6 kV 4H-SiC PiN Diodes for Power Module Switching Applications

Materials Science Forum ◽

10.4028/www.scientific.net/msf.527-529.1355 ◽

2006 ◽

Vol 527-529 ◽

pp. 1355-1358 ◽

Cited By ~ 1

Author(s):

Brett A. Hull ◽

Mrinal K. Das ◽

Jim Richmond ◽

Bradley Heath ◽

Joseph J. Sumakeris ◽

...

Keyword(s):

Pin Diode ◽

High Current ◽

Power Module ◽

Temperature Dependent ◽

Forward Voltage ◽

Pin Diodes ◽

Blocking Voltage ◽

Chip Size ◽

Switching Characteristics ◽

Vf Drift

Forward voltage (VF) drift, in which a 4H-SiC PiN diode suffers from an irreversible increase in VF under forward current flow, continues to inhibit commercialization of 4H-SiC PiN diodes. We present our latest efforts at fabricating high blocking voltage (6 kV), high current (up to 50 A) 4H-SiC PiN diodes with the best combination of reverse leakage current (IR), forward voltage at rated current (VF), and VF drift yields. We have achieved greater than 60% total die yield onwafer for 50 A diodes with a chip size greater than 0.7 cm2. A comparison of the temperature dependent conduction and switching characteristics between a 50 A/6 kV 4H-SiC PiN diode and a commercially available 60 A/4.5 kV Si PiN diode is also presented.

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Investigation of Forward Voltage Degradation due to Process-Induced Defects in 4H-SiC MOSFET

Materials Science Forum ◽

10.4028/www.scientific.net/msf.924.365 ◽

2018 ◽

Vol 924 ◽

pp. 365-368 ◽

Cited By ~ 3

Author(s):

Kumiko Konishi ◽

Ryusei Fujita ◽

Yuki Mori ◽

Akio Shima

Keyword(s):

High Reliability ◽

Stress Test ◽

Implantation Dose ◽

Imaging Method ◽

Stress Tests ◽

Forward Voltage ◽

Current Stress ◽

Before And After ◽

Induced Defects ◽

Voltage Degradation

We investigated process induced defects at various ion implantation conditions, and evaluated forward voltage degradation of body diode in 3.3 kV SiC MOSFET. First, by using photoluminescence (PL) observation, we evaluated the formation level of Basal Plane Dislocations (BPD) induced by Al implantation and anneal process with various Al implantation dose. Second, 3.3 kV double-diffused SiC MOSFETs were fabricated and forward current stress tests were performed to body diodes in SiC MOSFETs. Then, electrical characteristics of SiC MOSFETs before and after the stress test were measured, and expanded Stacking faults (SFs) in SiC epitaxial layer after the stress test were observed by PL imaging method. These results indicate that low dose or high temperature Al implantation conditions can suppress the formation of BPDs, and SiC MOSFETs fabricated using optimized Al implantation conditions show high reliability under current stress test.

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Comparative Evaluation of Forward Voltage Degradation due to Propagating and Converted Basal Plane Dislocations

Materials Science Forum ◽

10.4028/www.scientific.net/msf.924.143 ◽

2018 ◽

Vol 924 ◽

pp. 143-146 ◽

Cited By ~ 3

Author(s):

Yoshitaka Nishihara ◽

Koji Kamei ◽

Kenji Momose ◽

Hiroshi Osawa

Keyword(s):

Strong Correlation ◽

Basal Plane ◽

Comparative Evaluation ◽

Epitaxial Layers ◽

Forward Voltage ◽

Pin Diodes ◽

Forward Current ◽

Voltage Degradation ◽

The Relationship ◽

Drift Layer

This study investigated the relationship between the forward voltage degradation induced by SSF expansion and (a) BPD density in substrates and epitaxial layers of SiC, and (b) the temperature during the application forward current to the pin diodes. The Vf shift caused by the BPDs in the drift layer simply depended on the BPD density. However, no correlation was initially observed between the Vf shift and BPD density in the substrate; instead a strong correlation was observed between the Vf shift and the device temperature measured when applying the current stress. Thus when we selected samples which show the same temperature at that time, a correlation was observed between the Vf shift and the BPD density in the SiC substrate, with the slope corresponding to the former, drift layer relationship. Therefore, due to the high BPD density in the SiC substrate, suppressing the Vf shift due to BPD density in this region is highly important, and a combination of approaches is therefore proposed in order to reduce the overall forward voltage degradation.

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