Evaluation of Suppressing Forward Voltage Degradation by Using a Low BPD Density Substrate or an Epitaxial Wafer with an HNDE

2020 ◽  
Vol 1004 ◽  
pp. 439-444
Author(s):  
Yoshitaka Nishihara ◽  
Koji Kamei ◽  
Kenji Momose ◽  
Hiroshi Osawa
Keyword(s):  
Field Effect Transistor ◽  
Minority Carrier ◽  
Oxide Semiconductor ◽  
Pin Diode ◽  
Forward Voltage ◽  
Carrier Recombination ◽  
Crucial Problem ◽  
Basal Plane Dislocation ◽  
Effect Transistor ◽  
Voltage Degradation

Forward voltage degradation is a crucial problem that must be overcome if we are to fabricate a metal-oxide semiconductor field-effect transistor (MOSFET) including a pin diode (PND) as a body diode in a silicon carbide (SiC). Previously, the basal plane dislocation (BPD) in a SiC substrate have been reduced to suppress bipolar degradation. On the other hand, an highly N-doped epilayer (HNDE) was recently fabricated that enhances the minority carrier recombination before the carrier arrives at the substrate. Although both approaches can reduce the Vf shift caused by the degradation, they should be used under different substrate conditions. When a substrate with a high BPD density is used for epitaxial growth, an HNDE is needed to realize a high-quality epitaxial wafer; however, the HNDE should not be formed on a substrate with a low BPD density.

Detecting Basal Plane Dislocations Converted in Highly Doped Epilayers

2019 ◽  
Vol 963 ◽  
pp. 272-275
Author(s):  
Yoshitaka Nishihara ◽  
Koji Kamei ◽  
Kenji Momose ◽  
Hiroshi Osawa
Keyword(s):  
Silicon Carbide ◽  
Basal Plane ◽  
Near Infrared ◽  
Minority Carrier ◽  
Pin Diode ◽  
Forward Voltage ◽  
Carrier Recombination ◽  
Near Ultraviolet ◽  
Bipolar Devices ◽  
Voltage Degradation

Suppression of the forward voltage degradation is essential in fabricating bipolar devices on silicon carbide. Using a highly N–doped 4H–epilayer as an enhancing minority carrier recombination layer is a powerful tool for reducing the expansion of BPDs converted at the epi/sub interface; however, these BPDs cannot be observed by using the near–infrared photoluminescence in the layer. Near–ultraviolet photoluminescence was instead used to detect BPDs as dark lines. In addition, a short BPD converted near the epi/sub interface and contributing to the degradation was detected. When this evaluation was applied to the fabrication of a pin diode including a highly N–doped 4H–epilayer, the Vf shift was suppressed in comparison with that in a diode without the layer.

Highly Efficient Switching Operation of 1.2 kV-Class SiC SWITCH-MOS

2020 ◽  
Vol 1004 ◽  
pp. 795-800 ◽  
Author(s):  
Masakazu Okada ◽  
Teruaki Kumazawa ◽  
Yusuke Kobayashi ◽  
Masakazu Baba ◽  
Shinsuke Harada
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Short Circuit ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Pin Diode ◽  
Switching Operation ◽  
Turn On ◽  
Switching Losses ◽  
Effect Transistor

A 1.2 kV silicon carbide (SiC) SBD-wall-integrated trench metal oxide semiconductor field effect transistor (MOSFET) (SWITCH-MOS) exhibits potential for solving body-PiN-diode-related problems such as bipolar forward degradation and switching losses among relatively low breakdown voltage 1.2 kV-class SiC MOSFETs. In this study, dynamic characteristics and switching losses of the SWITCH-MOS and conventional MOSFET are compared. The results demonstrate that the SWITCH-MOS exhibits smaller turn-on and reverse recovery losses than a conventional MOSFET at high temperatures. Ruggedness performances such as short circuit and unclamped inductive switching capabilities were evaluated.

Numerical Simulations of a 4H-SiC BMFET Power Transistor with Normally-Off Characteristics

2011 ◽  
Vol 679-680 ◽  
pp. 621-624 ◽  
Author(s):  
Francesco Giuseppe Della Corte ◽  
Fortunato Pezzimenti ◽  
Salvatore Bellone ◽  
Roberta Nipoti
Keyword(s):  
Field Effect Transistor ◽  
Minority Carrier ◽  
Physical Models ◽  
Carrier Injection ◽  
Carrier Recombination ◽  
Mode Field ◽  
Bipolar Mode ◽  
Recombination Processes ◽  
Effect Transistor ◽  
Fundamental Physical

A numerical simulation study focused on an oxide-free 4H-SiC power device that is based on a normally-off Bipolar Mode Field Effect Transistor (BMFET) structure, and therefore on the principle of conductivity modulation from minority carrier injection, is presented. Starting from a n-/n+ 4H-SiC epi-wafer, with an epitaxial layer thickness of a few microns, and considering the presently available 4H-SiC ion implantation technology, a completely planar SiC-based BMFET has been designed. Such a device has interesting features in terms of static forward and blocking I V characteristics for high power applications. The 4H-SiC fundamental physical models, such as the doping incomplete ionization and the carrier recombination processes, were taken into account during the simulations.

scholarly journals Ab initio perspective of ultra-scaled CMOS from 2D-material fundamentals to dynamically doped transistors

2021 ◽  
Vol 5 (1) ◽  
Author(s):  
Aryan Afzalian
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Field Effect Transistor ◽  
High Mobility ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Grand Challenge ◽  
Gate Length ◽  
Delay Performance ◽  
Effect Transistor

AbstractUsing accurate dissipative DFT-NEGF atomistic-simulation techniques within the Wannier-Function formalism, we give a fresh look at the possibility of sub-10-nm scaling for high-performance complementary metal oxide semiconductor (CMOS) applications. We show that a combination of good electrostatic control together with high mobility is paramount to meet the stringent roadmap targets. Such requirements typically play against each other at sub-10-nm gate length for MOS transistors made of conventional semiconductor materials like Si, Ge, or III–V and dimensional scaling is expected to end ~12 nm gate-length (pitch of 40 nm). We demonstrate that using alternative 2D channel materials, such as the less-explored HfS2 or ZrS2, high-drive current down to ~6 nm is, however, achievable. We also propose a dynamically doped field-effect transistor concept, that scales better than its MOSFET counterpart. Used in combination with a high-mobility material such as HfS2, it allows for keeping the stringent high-performance CMOS on current and competitive energy-delay performance, when scaling down to virtually 0 nm gate length using a single-gate architecture and an ultra-compact design (pitch of 22 nm). The dynamically doped field-effect transistor further addresses the grand-challenge of doping in ultra-scaled devices and 2D materials in particular.

scholarly journals Challenges and Perspectives for Vertical GaN-on-Si Trench MOS Reliability: From Leakage Current Analysis to Gate Stack Optimization

Materials ◽  
2021 ◽  
Vol 14 (9) ◽  
pp. 2316
Author(s):  
Kalparupa Mukherjee ◽  
Carlo De Santi ◽  
Matteo Borga ◽  
Karen Geens ◽  
Shuzhen You ◽  
...  
Keyword(s):  
Field Effect Transistor ◽  
Dynamic Performance ◽  
Power Conversion ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Current Analysis ◽  
Power Transistors ◽  
Trench Structure ◽  
Effect Transistor ◽  
Gan On Si

The vertical Gallium Nitride-on-Silicon (GaN-on-Si) trench metal-oxide-semiconductor field effect transistor (MOSFET) is a promising architecture for the development of efficient GaN-based power transistors on foreign substrates for power conversion applications. This work presents an overview of recent case studies, to discuss the most relevant challenges related to the development of reliable vertical GaN-on-Si trench MOSFETs. The focus lies on strategies to identify and tackle the most relevant reliability issues. First, we describe leakage and doping considerations, which must be considered to design vertical GaN-on-Si stacks with high breakdown voltage. Next, we describe gate design techniques to improve breakdown performance, through variation of dielectric composition coupled with optimization of the trench structure. Finally, we describe how to identify and compare trapping effects with the help of pulsed techniques, combined with light-assisted de-trapping analyses, in order to assess the dynamic performance of the devices.

scholarly journals 4H-SiC Double Trench MOSFET with Split Heterojunction Gate for Improving Switching Characteristics

Materials ◽  
2021 ◽  
Vol 14 (13) ◽  
pp. 3554
Author(s):  
Jaeyeop Na ◽  
Jinhee Cheon ◽  
Kwangsoo Kim
Keyword(s):  
Dynamic Characteristics ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Switching Loss ◽  
Switching Speed ◽  
Polysilicon Gate ◽  
Effect Transistor ◽  
Switching Characteristics

In this paper, a novel 4H-SiC split heterojunction gate double trench metal-oxide-semiconductor field-effect transistor (SHG-DTMOS) is proposed to improve switching speed and loss. The device modifies the split gate double trench MOSFET (SG-DTMOS) by changing the N+ polysilicon split gate to the P+ polysilicon split gate. It has two separate P+ shielding regions under the gate to use the P+ split polysilicon gate as a heterojunction body diode and prevent reverse leakage `current. The static and most dynamic characteristics of the SHG-DTMOS are almost like those of the SG-DTMOS. However, the reverse recovery charge is improved by 65.83% and 73.45%, and the switching loss is improved by 54.84% and 44.98%, respectively, compared with the conventional double trench MOSFET (Con-DTMOS) and SG-DTMOS owing to the heterojunction.

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