A 3 GHz Semi-Digital Delay Locked Loop with High Resolution
2014 ◽
Vol 571-572
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pp. 881-884
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A high speed and high resolution semi-digital DLL (Delay Locked Loop) circuit will be discussed. The circuit is composed of three blocks: delay line, phase detector and digital finite-state machine (FSM). The delay line consists of two steps: the coarse tuning by tapping and the fine delay using interpolation to enable a resolution as high as 2 picoseconds. With the two steps approach and configuration of delay line, 3 GHz speed and picoseconds-level resolution can be achieved.
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2012 ◽
pp. 144-151
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2015 ◽
Vol 24
(07)
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pp. 1550101
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2003 ◽
Vol 21
(4)
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pp. 501-512
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2020 ◽
Vol 9
(2)
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pp. 1179-1183
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2004 ◽
Vol 51
(11)
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pp. 635-639
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