Automatic Feature Recognition for Data Interoperability Issues in High-Speed Electronics System Design

2008 ◽  
Author(s):  
Xiaolin Chen ◽  
Hui Zhang ◽  
Will Miller
Keyword(s):  
System Design ◽  
Design Process ◽  
High Speed ◽  
High Performance ◽  
Feature Recognition ◽  
Circuit Simulation ◽  
Signal Integrity ◽  
Electronic Systems ◽  
Design Data ◽  
Automatic Feature Recognition

Technology trends toward higher speed and density devices have pushed high performance electronic system design to its limits. With fine miniaturization of very-large-scale integrated (VLSI) circuits and rapid increase in the working frequency of system-on-a-chip (SoC), the signal integrity has become a major concern. As the operating frequencies enter the gigahertz range, signal integrity issues such as cross talk, power-ground-plane voltage bounce, and substrate losses can no longer be neglected. In order to design high-performance electronic systems with fast time-to-market, it is often needed to analyze whole or part of the system at one fundamentally deeper level of physics. It has begun to be recognized that electromagnetic (EM) field analysis needs to be rigorously included as an addition to traditional circuit simulation. A common problem in this practice is the lack of efficient tools that enable engineers to easily transfer circuit board design data into EM solvers. To partially solve this problem, ACIS SAT has been introduced as a standard data exchange format and been adopted by many software vendors for data import and export. However, efficient data transfer remains a problem as the geometry created in the design package becomes static and no longer feature-based once imported into the simulation package. In this paper, automatic feature recognition algorithms are implemented to help extract features and parameters from the imported static model in SAT format. Case studies will be provided for some representative high speed electronics designs. This work is supported by Research & Technology Development Grant Program of Washington Technology Center with a goal to achieve improved design process for high-speed electronic systems. The developed tool has a potential to speed up the current design process by eliminating laborious manual preparation of design data for EM simulation and allow what-if analysis to be automated to highlight likely signal integrity issues.

Some Noteworthy Aspects in Designing High-Speed PCB

2013 ◽  
Vol 662 ◽  
pp. 846-850
Author(s):  
Jiang Hong ◽  
Zhi Wei Tang ◽  
Long Hu Chen
Keyword(s):  
System Design ◽  
Integrated Circuit ◽  
High Speed ◽  
Electromagnetic Compatibility ◽  
Signal Integrity ◽  
Design Rules ◽  
Pcb Design ◽  
Key Factor ◽  
Switch Rate ◽  
The Cost

With the increase of integrated circuit switch rate and PCB density, signal integrity has become one of the problems must be concerned in high-speed PCB design. How to fully consider EMC (Electromagnetic compatibility) and take effective measures has been a key factor of a system design. Based on the consideration of EMC, the author put forward some aspects in designing high-speed PCB. The optimized PCB design rules have steady and credible performance, the development period is shortened and the cost is reduced. The conclusions drawn from the dissertation are helpful to the design of high-speed PCB.

High Performance Materials and Devices for High-Speed Electronic Systems

10.1142/11156 ◽  
2018 ◽  
Author(s):  
F Jain ◽  
C Broadbridge ◽  
H Tang ◽  
M Gherasimova
Keyword(s):  
High Speed ◽  
High Performance ◽  
Electronic Systems

SerDes Design and Modeling over 25+ Gb/s Serial Link

2011 ◽  
Vol 2011 (1) ◽  
pp. 000044-000060
Author(s):  
Pervez M. Aziz ◽  
Adam Healey ◽  
Cathy Liu ◽  
Freeman Zhong ◽  
Alex Zabroda
Keyword(s):  
High Speed ◽  
Forward Error Correction ◽  
Circuit Simulation ◽  
Signal Integrity ◽  
Systems Modeling ◽  
Behavioral Models ◽  
Noisy Environments ◽  
Serial Link ◽  
Link Performance ◽  
Forward Error

In this paper, signal integrity challenges for high speed serial link at 25 Gb/s, such as lossy channels and noisy environments are discussed. A few solution spaces to address those challenges are investigated, such as advanced equalization schemes, alternative signaling formats and forward error correction. It demonstrates that advanced signal processing enables long reach and extra long reach serial link performance at 25 Gb/s in next generation systems. Modeling methodologies used in SerDes behavioral models to ensure good correlation with transistor level circuit simulation are also discussed.

Superconducting Interconnections in Future High Performance Systems

1987 ◽  
Vol 108 ◽  
Author(s):  
R. C. Frye
Keyword(s):  
Critical Current ◽  
High Speed ◽  
High Performance ◽  
Electronic Systems ◽  
Maximum Current Density ◽  
Maximum Current ◽  
High Performance Systems ◽  
Current Densities ◽  
Very High ◽  
Scaling Rule

ABSTRACTNew, high temperature superconducting materials could eventually be used for interconnections in electronic systems. Such interconnections would undoubtedly cost more to implement than conventional ones, so the most likely applications would be for complex, high-speed systems that could benefit from the performance advantages of a resistance-free interconnecting medium. The problem with conventional conductors in these systems is that the resistance of wires increases quadratically as dimensions are scaled down. The most important advantage offered by superconductors is that they are not linked to this scaling rule. Their principal limitation is the maximum current density that they will support and this determines the range of applications for which they are superior to conventional conductors. An analysis will be presented which examines the relative advantages of superconductors for different critical current densities, wire dimensions and system sizes.If their critical current densities are adequate, and if they can statisfy a number of processing criteria, then superconductors could find useful applications in a number of high performance electronic systems. The most likely applications will be those demanding very high interconnection densities. Several of these systems will be discussed.

scholarly journals High-performance FPGA implementation of the secure hash algorithm 3 for single and multi-message processing

2022 ◽  
Vol 12 (2) ◽  
pp. 1324
Author(s):  
Fatimazahraa Assad ◽  
Mohamed Fettach ◽  
Fadwa El Otmani ◽  
Abderrahim Tragha
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
High Performance ◽  
Message Processing ◽  
Maximum Throughput ◽  
Design Data ◽  
Hash Algorithm ◽  
Field Programmable ◽  
Secure Hash Algorithm ◽  
Hardware Description

<span>The secure hash function has become the default choice for information security, especially in applications that require data storing or manipulation. Consequently, optimized implementations of these functions in terms of Throughput or Area are in high demand. In this work we propose a new conception of the secure hash algorithm 3 (SHA-3), which aim to increase the performance of this function by using pipelining, four types of pipelining are proposed two, three, four, and six pipelining stages. This approach allows us to design data paths of SHA-3 with higher Throughput and higher clock frequencies. The design reaches a maximum Throughput of 102.98 Gbps on Virtex 5 and 115.124 Gbps on Virtex 6 in the case of the 6 stages, for 512 bits output length. Although the utilization of the resource increase with the increase of the number of the cores used in each one of the cases. The proposed designs are coded in very high-speed integrated circuits program (VHSIC) hardware description language (VHDL) and implemented in Xilinx Virtex-5 and Virtex-6 A field-programmable gate array (FPGA) devices and compared to existing FPGA implementations.</span>

DIMM-in-a-PACKAGE (DIAP) signal integrity for high-performance on-board memory applications

2013 ◽  
Vol 2013 (1) ◽  
pp. 000223-000227 ◽  
Author(s):  
Zhuowen Sun ◽  
Kevin Chen ◽  
Richard Crisp
Keyword(s):  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
Signal Integrity ◽  
Bottom Layer ◽  
Data Rate ◽  
Optimization Techniques ◽  
Network Computing ◽  
Memory Applications ◽  
Type 3

The recent explosion of thin notebooks and tablets has challenged the IC packaging industry to come up with new solutions of DRAM integration onto motherboard. Beyond traditional SO-DIMMs, innovative memory solutions should perform well at high speed (1600 MT/s) with much reduced footprint and z-height, while leveraging current manufacturing infrastructure for lower cost and also enabling simpler and cheaper motherboard design. To accomplish all the goals stated above for high-performance on-board memory applications, we showed a new DIMM-in-a-Package (DIAP) technology. This 22.5×17.5×1.2mm quad-die face-down (QFD) part has four standard center bond DDR3L dies (each ×16) face-down, which are wire-bonded to the bottom layer of the 407-ball BGA package. This judiciously designed package places data nets at the peripheral and command/control/address nets in the middle of the BGA. As such, motherboard design and layout were substantially simplified to allow the use of low-cost non-HDI Type 3 board for signal integrity performance comparable to expensive HDI boards. The QFD™ ball assignment could accommodate future memory density expansion and different memory type (e.g. LPDDR3, DDR4). It also enables dual-rank operations in each channel when double-sided assembly is used. We successfully demonstrated in production build that 1GB ×64 DDR3L QFD with data rate of 1600 MT/s can be achieved on a Type 3 motherboard for the Intel Haswell mobile platform in dual-channel dual-rank operation. A balanced-T Command/Address topology between the processor and the memory was implemented in a DELL XPS 12 Ultrabook. Channel simulations including chip, package and board were performed. We also conducted cross-talk analysis up to 9 aggressors to take into account the timing impact from the dense routing inside QFD. Layout optimization techniques for best signal integrity, such as trace length matching and stub length minimization, were discussed in detail and applied to both package and motherboard design. Lastly, we also presented and discussed DIAPs currently under study with different memory bus topologies for even higher data rate up to 2400 MT/s using the same QFD technology. Our results and analysis demonstrated DIAP using wirebond-based QFD technology as a viable candidate for the compact, low-cost, high-performance on-board memory solution. We have identified several key aspects of DIAP architecture design and physical layout that are strongly impacting the SI of QFD parts at rate &gt;1600 MT/s and that could be optimized for DDR4 operations. QFD DIAP can become an attractive low-cost, high-performance option for many OEMs and ODMs in various mobile, personal and network computing platforms.

High Performance Logic and Circuits for High-Speed Electronic Systems

10.1142/11502 ◽  
2019 ◽  
Author(s):  
F Jain ◽  
C Broadbridge ◽  
M Gherasimova ◽  
H Tang
Keyword(s):  
High Speed ◽  
High Performance ◽  
Electronic Systems
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