scholarly journals Design of a Low on Resistance High Voltage (120V) Novel 3D NLDMOS with Side Isolation Based on 0.35um BCD Process Technology

2018 ◽  
Vol 201 ◽  
pp. 02004
Author(s):  
Shao-Ming Yang ◽  
Gene Sheu ◽  
Tzu Chieh Lee ◽  
Ting Yao Chien ◽  
Chieh Chih Wu ◽  
...  
Keyword(s):  
Breakdown Voltage ◽  
High Voltage ◽  
High Performance ◽  
Power Device ◽  
Simulation Tool ◽  
Process Technology ◽  
Surface Field ◽  
Kirk Effect ◽  
Tcad Simulation ◽  
Reduced Surface

High performance power device is necessary for BCD power device. In this paper, we used 3D Synopsis TCAD simulation tool Sentaurus to develop 120V device and successfully simulated. We implemented in a conventional 0.35um BCDMOS process to present of a novel high side 120V LDMOS have reduced surface field (RESURF) and Liner p-top structure with side isolation technology. The device has been research to achieve a benchmark specific on-resistance of 189 mΩ-mm2 while maintaining horizontal breakdown voltage and vertical isolation voltage both to target breakdown voltage of 120V. In ESOA, we also proposed a better performance of both device without kirk effect.

Designing of Quasi-Modulated Region in 4H-SiC Lateral RESURF MOSFETs

2014 ◽  
Vol 778-780 ◽  
pp. 943-946
Author(s):  
Yuichiro Nanen ◽  
Jun Suda ◽  
Tsunenobu Kimoto
Keyword(s):  
Silicon Carbide ◽  
Metal Oxide ◽  
Breakdown Voltage ◽  
High Voltage ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Surface Field ◽  
Reduced Surface

Characteristics of high-voltage lateral silicon carbide metal-oxide-semiconductor field-effect transistors (MOSFETs) with various reduced surface field (RESURF) structures were simulated. Breakdown voltage was enhanced from 5300 V for single-zone RESURF to 7400 V for two-zone, and to 7600 V for quasi-modulated RESURF MOSFETs.

Wide Bandgap Semiconductor Power Devices

1997 ◽  
Vol 483 ◽  
Author(s):  
T. P. Chow ◽  
N. Ramungul ◽  
M. Ghezzo
Keyword(s):  
High Voltage ◽  
Wide Bandgap ◽  
Power Device ◽  
Experimental Demonstration ◽  
Power Devices ◽  
Process Technology ◽  
Power Semiconductor ◽  
Wide Bandgap Semiconductor ◽  
Simulated Performance ◽  
Device Structures

AbstractThe present status of high-voltage power semiconductor switching devices is reviewed. The choice and design of device structures are presented. The simulated performance of the key devices in 4H-SiC is described. The progress in high-voltage power device experimental demonstration is described. The material and process technology issues that need to be addressed for device commercialization are discussed.

Comparative Study of SiC MOSFETs in High Voltage Switching Operation

2012 ◽  
Vol 717-720 ◽  
pp. 1081-1084 ◽  
Author(s):  
Tsuyoshi Funaki ◽  
Yuki Nakano ◽  
Takashi Nakamura
Keyword(s):  
Breakdown Voltage ◽  
High Voltage ◽  
Current Density ◽  
Power Device ◽  
Resistive Load ◽  
Density Condition ◽  
Switching Speed ◽  
Switching Operation ◽  
Switching Performance ◽  
Turn On

SiC power device is expected to have high breakdown voltage with low on resistance, which cannot be attainable for conventional Si device. This study evaluates the switching performance of high voltage SiC MOSFETs with comparing to that of conventional Si power MOSFET having equivalent breakdown voltage. To this end, turn-on and turn-off switching operation of MOSFETs are assessed with resistive load for same conduction current density. Though the on resistance of SiC MOSFETs are quite lower than Si MOSFET, especially for trench gate type. But, SiC MOSFETs have larger terminal capacitance. Therefore, SiC MOSFETs show slower switching speed than Si MOSFETs for same current density condition.

A New Slope SOI-LDMOS High-Voltage Power Device

2012 ◽  
Vol 236-237 ◽  
pp. 797-800
Author(s):  
Xiao Ming Yang ◽  
Yu Cai ◽  
Tian Qian Li
Keyword(s):  
Oxide Layer ◽  
Breakdown Voltage ◽  
High Voltage ◽  
Power Device ◽  
Drift Region ◽  
Electrical Field ◽  
New Device ◽  
Buried Oxide ◽  
Drain Electrode ◽  
Surface Electric Field

A slope SOI-LDMOS power device is proposed for high-voltage. When a positive bais is applied to the drain electrode, holes are induced and astricted by the slope buried oxide layer. So a high density positive charge layer is formed on the buried oxide layer. The electrical field in the buried oxide is improved as well as vertical breakdown voltage by the layer. Because the thickness of the drift region linearly increases from the source to the drain, the surface electric field is optimized, resulting in increase of lateral breakdown voltage. In this paper, the electric characteristics of the new device are simulated by Medici softerware. The result is shown that above 600 V breakdown voltage is obtained at 1μm thick buried oxide layer. The breakdown voltage is higher by three times than that of conventional SOI LDMOS.

scholarly journals Improvement in Turn-Off Loss of the Super Junction IGBT with Separated n-Buffer Layers

Micromachines ◽  
2021 ◽  
Vol 12 (11) ◽  
pp. 1422
Author(s):  
Ki-Yeong Kim ◽  
Joo-Seok Noh ◽  
Tae-Young Yoon ◽  
Jang-Hyun Kim
Keyword(s):  
Breakdown Voltage ◽  
Computer Aided Design ◽  
Buffer Layers ◽  
Simulation Tool ◽  
Electrical Characteristics ◽  
Insulated Gate Bipolar Transistor ◽  
Computer Aided ◽  
Long Time ◽  
Tcad Simulation ◽  
Aided Design

In this study, we propose a super junction insulated-gate bipolar transistor (SJBT) with separated n-buffer layers to solve a relatively long time for carrier annihilation during turn-off. This proposition improves the turn-off characteristic while maintaining similar on-state characteristics and breakdown voltage. The electrical characteristics of the devices were simulated by using the Synopsys Sentaurus technology computer-aided design (TCAD) simulation tool, and we compared the conventional SJBT with SJBT with separated n-buffer layers. The simulation tool result shows that turn-off loss (Eoff) drops by about 7% when on-state voltage (Von) and breakdown voltage (BV) are similar. Von increases by about 0.5% and BV decreases by only about 0.8%.

Influence of Lateral Straggling of Implated Aluminum Ions on High Voltage 4H-SiC Device Edge Termination Design

2018 ◽  
Vol 924 ◽  
pp. 361-364 ◽  
Author(s):  
Yi Fan Jiang ◽  
B. Jayant Baliga ◽  
Alex Q. Huang
Keyword(s):  
High Voltage ◽  
Doping Concentration ◽  
Secondary Electron ◽  
Electric Field Distribution ◽  
Simulation Tool ◽  
Edge Termination ◽  
Interface Charge ◽  
Aluminum Ions ◽  
Background Doping ◽  
Tcad Simulation

This paper presents the analysis of Aluminum profile implanted into 4H-SiC with low background doping concentration. A strong lateral straggling effect was discovered with secondary electron potential contrast (SEPC) method, and analyzed by Sentaurus Monto Carlo simulations. The effect of lateral straggling was included in the edge termination design using Sentaurus TCAD simulation tool, and the results are compared with design not including the lateral straggling effect. The effect of interface charge on the electric field distribution and breakdown voltage of different 10 kV device edge termination designs was compared and analyzed.

Highly Heat-Dissipating and High-Voltage SOI-LDMOS Power Device

2012 ◽  
Vol 614-615 ◽  
pp. 1574-1577
Author(s):  
Xiao Ming Yang ◽  
Yu Cai ◽  
Tian Qian Li
Keyword(s):  
Surface Temperature ◽  
Breakdown Voltage ◽  
High Voltage ◽  
Power Device ◽  
Drift Region ◽  
Type Layer ◽  
Simulation Results ◽  
Buried Layers ◽  
P Type ◽  
Maximum Surface Temperature

A highly heat-dissipating and high-voltage SOI-LDMOS power device is proposed. Its substrate was selectively etched, like the Camsemi SOI, so breakdown voltage was decided only by lateral breakdown voltage. A p-type layer and a Si3N4 buried layers were introduced into the new structure for lowering specific on-resistance and temperature. The simulation results show that breakdown voltage is 747 V at the 37 μm length of the drift region, and specific on-resistance and maximum surface temperature are reduced by 94.48% and 15.43% than those of Camsemi SOI, respectively.

Lateral 4H-SiC MOSFETs with Low On-Resistance by Using Two-Zone Double RESURF Structure

2007 ◽  
Vol 556-557 ◽  
pp. 815-818
Author(s):  
Masato Noborio ◽  
Jun Suda ◽  
Tsunenobu Kimoto
Keyword(s):  
Temperature Dependence ◽  
Breakdown Voltage ◽  
Figure Of Merit ◽  
Device Simulation ◽  
Gate Oxide ◽  
Dose Optimization ◽  
High Breakdown Voltage ◽  
Surface Field ◽  
Reduced Surface

4H-SiC lateral MOSFETs with a double reduced surface field (RESURF) structure have been fabricated in order to reduce drift resistance. A two-zone RESURF structure was also employed in addition to double RESURF structure for achieving both high breakdown voltage and low on-resistance. After device simulation for dose optimization, 4H-SiC two-zone double RESURF MOSFETs have been fabricated. The fabricated MOSFETs block 1380 V and exhibit a low on-resistance of 66 m1cm2 (including a drift resistance of 24 m1cm2) at a gate oxide field of 3 MV/cm. The figure-of-merit of present device is about 29 MW/cm2, which is the best performance among any lateral MOSFETs. The drift resistance of the fabricated double RESURF MOSFETs is only 50 % or even lower than that of single RESURF MOSFETs. Temperature dependence of device characteristics is also discussed.

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