Research about Subsynchronous Oscillation Caused by High-Voltage-Direct-Current

2013 ◽  
Vol 805-806 ◽  
pp. 920-925
Author(s):  
Nan Zhou ◽  
Guan Rong Wang
Keyword(s):  
Subsynchronous Oscillation ◽  
Hvdc System ◽  
High Voltage Direct Current ◽  
Turbine Generators ◽  
Electrical Instability ◽  
Electrical Damping ◽  
Oscillation Frequencies ◽  
Damping Torque ◽  
System Frequency ◽  
Shaft Failure

Torsional interaction exists between HVDC converters and turbine-generators, and negative electrical damping provided by HVDC may cause subsynchronous oscillation (SSO) that can lead to turbine-generator shaft failure and electrical instability at oscillation frequencies lower than the fundamental system frequency. This paper makes a preliminary inquiry about the subsynchronous oscillation mechanism caused by the HVDC system, and puts forward Subsynchronous Damping Controller, and eventually makes a damping synchronous oscillation of the electrical Damping torque increment out of the generator electromagnetic torque to suppressing SSO.

Analysis of Sub-Synchronous Oscillation (SSO) Caused by HVDC Transmission System

2014 ◽  
Vol 960-961 ◽  
pp. 1243-1247
Author(s):  
Yang Cheng Xiang Song ◽  
Jun Luo ◽  
Shu Jun Yao
Keyword(s):  
Power Systems ◽  
Synchronous Oscillation ◽  
Hvdc System ◽  
Hvdc Transmission ◽  
Electrical Instability ◽  
Turbo Generator ◽  
Model Research ◽  
Electrical Engineers ◽  
Shaft Failure ◽  
Digital Time

Sub-synchronous oscillation (SSO) caused by highly non-linear HVDC devices can lead to shaft failure and electrical instability of a turbo-generator at oscillation frequency lower than power grid frequency. With increasing HVDC installed in power systems, analysis of SSO becomes a great concern of electrical engineers. In this paper, the reason and process of the SSO are presented by analyzing equations of the mass-springs model. Research methods of SSO are reviewed in HVDC system. And advantages of digital time-domain simulation are demonstrated through combining with algorithm of Prony.

Damping Analysis of Subsynchronous Oscillation Caused by HVDC

2013 ◽  
Vol 732-733 ◽  
pp. 1065-1068
Author(s):  
Shi Wu Xiao ◽  
Lan Lan Shu
Keyword(s):  
Time Domain ◽  
Test Signal ◽  
Subsynchronous Oscillation ◽  
High Voltage Direct Current ◽  
Damping Characteristics ◽  
Torque Coefficient ◽  
Machine Systems ◽  
Electrical Damping ◽  
The Time Domain ◽  
Signal Method

High Voltage Direct Current transmission (HVDC) will cause torsional interaction under certain conditions. Among a variety of factors, improper rectifier control has fateful effect. In the paper, the test signal method which is the time-domain form of the complex torque coefficient approach (CTC approach) is studied. Its application conditions in multi-machine systems are summarized. Using the test signal method, impacts of DC power, DC voltage, rectifier controller parameters and generator output on electrical damping characteristics in the Suizhong system are studied based on time-domain simulation model.

Study of HVDC System and Subsynchronous Oscillation

2015 ◽  
Vol 1092-1093 ◽  
pp. 356-361
Author(s):  
Peng Fei Zhang ◽  
Lian Guang Liu
Keyword(s):  
Power Plant ◽  
Time Domain ◽  
Simulation Method ◽  
Time Domain Simulation ◽  
Stable Convergence ◽  
Turbine Generator ◽  
Plant Model ◽  
Subsynchronous Oscillation ◽  
Hvdc System ◽  
Simulation Results

With the application and development of Power Electronics, HVDC is applied more widely China. However, HVDC system has the possibilities to cause subsynchronous torsional vibration interaction with turbine generator shaft mechanical system. This paper simply introduces the mechanism, analytical methods and suppression measures of subsynchronous oscillation. Then it establishes a power plant model in islanding model using PSCAD, and analyzes the effects of the number and output of generators to SSO, and verifies the effect of SEDC and SSDC using time-domain simulation method. Simulation results show that the more number and output of generators is detrimental to the stable convergence of subsynchronous oscillation, and SEDC、SSDC can restrain unstable SSO, avoid divergence of SSO, ensure the generators and system operate safely and stably

Real power regulation design for multi-terminal VSC-HVDC systems

2013 ◽  
Vol 3 (2) ◽  
Author(s):  
Guo-Jie Li ◽  
Si-Ye Ruan ◽  
Tek Lie
Keyword(s):  
Control Strategy ◽  
Control Mode ◽  
Voltage Source ◽  
Voltage Source Converter ◽  
Real Power ◽  
The Real ◽  
Hvdc System ◽  
High Voltage Direct Current ◽  
Power Regulation ◽  
Regulation Functions

AbstractA multi-terminal voltage-source-converter (VSC) based high voltage direct current (HVDC) system is concerned for its flexibility and reliability. In this study, a control strategy for multiple VSCs is proposed to auto-share the real power variation without changing control mode, which is based on “dc voltage droop” power regulation functions. With the proposed power regulation design, the multiple VSCs automatically share the real power change and the VSC-HVDC system is stable even under loss of any one converter while there is no overloading for any individual converter. Simulation results show that it is effective to balance real power for power disturbance and thus improves operation reliability for the multi-terminal VSC-HVDC system by the proposed control strategy.

Research on SSO Caused by HVDC Based on Eigenvalue Analysis

2011 ◽  
Vol 383-390 ◽  
pp. 4792-4798
Author(s):  
Dan Zhang ◽  
Xiang Ning Xiao ◽  
Lin Yang ◽  
Ben Feng Gao
Keyword(s):  
Eigenvalue Analysis ◽  
Small Signal ◽  
Analysis Method ◽  
Subsynchronous Oscillation ◽  
Electromagnetic Transient ◽  
Hvdc System ◽  
Electromagnetic Transient Simulation ◽  
Linearized Model ◽  
Oscillation Characteristics ◽  
Oscillation Characteristic

Subsynchronous Oscillation problems caused by HVDC system are studied and analyzed intensively in this paper based on eigenvalue analysis method. By establishing the small signal linearized model of a typical HVDC system, subsynchronous oscillation characteristics of the system with or without SSDC are obtained. Further more, the influence of SSDC parameters to the system subsynchronous oscillation characteristic can be illustrated clearly. This is significant for SSDC design in order to achieve a satisfied restraining effect. Comparing with more accurate electromagnetic transient simulation results, the consistency of the two methods is verified and it can be demonstrated that eigenvalue analysis method is adequate for studying subsynchronous oscillations.

scholarly journals Modelling of the Power Interface of the Digital-Physical Hybrid Simulation System of a VSC-HVDC Based on Virtual Resistance Compensation

Electronics ◽  
2018 ◽  
Vol 7 (11) ◽  
pp. 333
Author(s):  
Jian Le ◽  
Hao Zhang ◽  
Cao Wang ◽  
Xingrui Li ◽  
Jiangfeng Zhu
Keyword(s):  
Current Source ◽  
Hybrid Simulation ◽  
Simulation System ◽  
System Stability ◽  
Interface Model ◽  
Simulation Accuracy ◽  
Hvdc System ◽  
High Voltage Direct Current ◽  
The Stability ◽  
Stability And Accuracy

To enhance the stability and accuracy of the digital-physical hybrid simulation system of a modular multilevel converter-based high voltage direct current (MMC-HVDC) system, this paper presents an improved power interface modeling algorithm based on ideal transformer method (ITM). By analyzing the stability condition of a hybrid simulation system based on the ITM model, the current of a so-called virtual resistance is added to the control signal of the controlled current source in the digital subsystem, and the stability of the hybrid simulation system with the improved power interface model is analyzed. The value of the virtual resistance is optimized by comprehensively considering system stability and simulation precision. A two-terminal bipolar MMC-HVDC simulation system based on the proposed power interface model is established. The comparisons of the simulation results verify that the proposed method can effectively improve the stability of the hybrid simulation system, and at the same time has the advantages of high simulation accuracy and easy implementation.

scholarly journals Research on Serial VSC-LCC Hybrid HVdc Control Strategy and Filter Design Scheme

Energies ◽  
2020 ◽  
Vol 13 (9) ◽  
pp. 2260
Author(s):  
Fan Cheng ◽  
Lijun Xie ◽  
Zhibing Wang
Keyword(s):  
Reactive Power ◽  
Filter Design ◽  
Control Strategies ◽  
Short Circuit ◽  
Voltage Source ◽  
Voltage Source Converter ◽  
Level Control ◽  
Hvdc System ◽  
High Voltage Direct Current ◽  
Design Scheme

This paper investigated the characteristics of a novel type of hybrid high voltage direct current (HVdc) converter, which is composed by line commutated converter series with voltage source converter. The system and valve level control strategies are introduced, which can provide ac system voltage support. A novel filter design scheme composed by resonant filers for hybrid HVdc are also proposed, which can decrease the capacity of reactive power compensation equipment without deteriorate harmonic characteristics. The ac voltage of HVdc fluctuation level caused by transmitted power variation will be effectively reduced, with the coordination between filter design scheme and converter control. In addition, the influence of ac grid strength is also analyzed by equivalent source internal impedance represented by short circuit ratio (SCR). Finally, the +800 kV/1600 MW hybrid HVdc system connecting two ac grids under different SCR cases are studied, and the PSCAD/EMTDC simulation results have validated the effectiveness for proposed strategy.

scholarly journals Minimum Short Circuit Ratio Requirement for MMC-HVDC Systems Based on Small-Signal Stability Analysis

Energies ◽  
2019 ◽  
Vol 12 (17) ◽  
pp. 3283 ◽  
Author(s):  
Zheren Zhang ◽  
Liang Xiao ◽  
Guoteng Wang ◽  
Jian Yang ◽  
Zheng Xu
Keyword(s):  
Reactive Power ◽  
Short Circuit ◽  
Small Signal ◽  
Small Signal Stability ◽  
Ratio Requirement ◽  
Planning Stage ◽  
Hvdc System ◽  
Hvdc Transmission ◽  
High Voltage Direct Current ◽  
Signal Stability

This paper determines the minimum short circuit ratio (SCR) requirement for a modular multilevel converter based high-voltage direct current (MMC-HVDC) transmission systems. Firstly, a simplified model of MMC is introduced; the MMC is represented by its AC and DC side equivalent circuit. Next, by linearizing the MMC subsystem and the DC network subsystem, the deduction of the small-signal models of MMC subsystem, the small-signal model of the DC network and MMC-HVDC are carried out successively. Thirdly, the procedure for determining the minimum SCR requirement of MMC-HVDC is described. Finally, case studies are performed on a two-terminal MMC-HVDC system under four typical control schemes. The results show that the restraint factors for the rectifier MMC is predominantly the voltage safety limit constraint, and the restraint factors for the inverter MMC are mainly the phase locked loop (PLL) or the outer reactive power controller. It is suggested that the minimum SCR requirement for the sending and the receiving systems should be 2.0 and 1.5 in the planning stage.

scholarly journals A Selective Fault Clearing Scheme for a Hybrid VSC-LCC Multi-Terminal HVdc System

Energies ◽  
2020 ◽  
Vol 13 (14) ◽  
pp. 3554
Author(s):  
Naushath M. Haleem ◽  
Athula D. Rajapakse ◽  
Aniruddha M. Gole ◽  
Ioni T. Fernando
Keyword(s):  
High Capacity ◽  
Voltage Source ◽  
Voltage Source Converter ◽  
Circuit Breakers ◽  
Hvdc System ◽  
Hvdc Transmission ◽  
High Voltage Direct Current ◽  
Clearing Functions ◽  
Transmission Structure ◽  
The Impact

A selective fault clearing scheme is proposed for a hybrid voltage source converter (VSC)-line commutated converter (LCC) multi-terminal high voltage direct current (HVdc) transmission structure in which two small capacity VSC stations tap into the main transmission line of a high capacity LCC-HVdc link. The use of dc circuit breakers (dc CBs) on the branches connecting to VSCs at the tapping points is explored to minimize the impact of tapping on the reliability of the main LCC link. This arrangement allows clearing of temporary faults on the main LCC line as usual by force retardation of the LCC rectifier. The faults on the branches connecting to VSC stations can be cleared by blocking insulated gate bipolar transistors (IGBTs) and opening ac circuit breakers (ac CB), without affecting the main line’s performance. A local voltage and current measurement based fault discrimination scheme is developed to identify the faulted sections and pole(s), and trigger appropriate fault recovery functions. This fault discrimination scheme is capable of detecting and discriminating short circuits and high resistances faults in any branch well before 2 ms. For the test grid considered, 6 kA, 2 ms dc CBs can easily facilitate the intended fault clearing functions and maintain the power transfer through healthy pole during single-pole faults.

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