Quantum Mechanical Analysis on Modeling of Surface Potential and Drain Current for Nanowire JLFET

2020 ◽  
Vol 64 ◽  
pp. 123-134
Author(s):  
N. Bora ◽  
N. Deka ◽  
R. Subadar
Keyword(s):  
Surface Potential ◽  
Silicon Layer ◽  
Drain Current ◽  
Mechanical Analysis ◽  
Quantum Mechanical ◽  
First Order ◽  
Charge Quantization ◽  
First Order Correction ◽  
Effect Transistor ◽  
Quantum Mechanical Effects

This paper presents an analytical model for ultra scaled symmetric double gate (SDG) nanowire junctionless field effect transistor (JLFET), which includes charge quantization in all the regions of operation. This model is based on a first-order correction for the confined energies obtained by solving the Schrodinger’s equation. The model is able to predict the quantum mechanical effects (QME) on the surface potential, drain current and transconductance for a highly doped and extremely thin silicon layer of thickness down to 4nm. The results obtained are validated by comparing with GENIUS 3D TCAD quantum simulations.

Quantum Modelling of Nanoscale Silicon Gate-All-Around Field Effect Transistor

2020 ◽  
Vol 64 ◽  
pp. 115-122
Author(s):  
P. Vimala ◽  
N.R. Nithin Kumar
Keyword(s):  
Analytical Model ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Inversion Layer ◽  
Drain Current ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Effect Transistor ◽  
Quantum Mechanical Effects ◽  
Novel Devices

The paper introduces an analytical model for gate all around (GAA) or Surrounding Gate Metal Oxide Semiconductor Field Effect Transistor (SG-MOSFET) inclusive of quantum mechanical effects. The classical oxide capacitance is replaced by the capacitance incorporating quantum effects by including the centroid parameter. The quantum variant of inversion charge distribution function, inversion layer capacitance, drain current, and transconductance expressions are modeled by employing this model. The established analytical model results agree with the simulated results, verifying these models' validity and providing theoretical supports for designing and applying these novel devices.

scholarly journals Metal oxide-graphene field-effect transistor: interface trap density extraction model

2016 ◽  
Vol 7 ◽  
pp. 1368-1376 ◽  
Author(s):  
Faraz Najam ◽  
Kah Cheong Lau ◽  
Cheng Siong Lim ◽  
Yun Seop Yu ◽  
Michael Loong Peng Tan
Keyword(s):  
Surface Potential ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Current Model ◽  
Drain Current ◽  
Interface Trap ◽  
Accurate Calculation ◽  
Trap Charge ◽  
Graphene Field Effect Transistor ◽  
Effect Transistor

A simple to implement model is presented to extract interface trap density of graphene field effect transistors. The presence of interface trap states detrimentally affects the device drain current–gate voltage relationship I ds–V gs. At the moment, there is no analytical method available to extract the interface trap distribution of metal-oxide-graphene field effect transistor (MOGFET) devices. The model presented here extracts the interface trap distribution of MOGFET devices making use of available experimental capacitance–gate voltage C tot–V gs data and a basic set of equations used to define the device physics of MOGFET devices. The model was used to extract the interface trap distribution of 2 experimental devices. Device parameters calculated using the extracted interface trap distribution from the model, including surface potential, interface trap charge and interface trap capacitance compared very well with their respective experimental counterparts. The model enables accurate calculation of the surface potential affected by trap charge. Other models ignore the effect of trap charge and only calculate the ideal surface potential. Such ideal surface potential when used in a surface potential based drain current model will result in an inaccurate prediction of the drain current. Accurate calculation of surface potential that can later be used in drain current model is highlighted as a major advantage of the model.

A Surface Potential-Based Model for Dual Gate Bilayer Graphene Field Effect Transistor Including the Capacitive Effects

2019 ◽  
Vol 28 (14) ◽  
pp. 1950241
Author(s):  
Sudipta Bardhan ◽  
Manodipan Sahoo ◽  
Hafizur Rahaman
Keyword(s):  
Surface Potential ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Drain Current ◽  
Bilayer Graphene ◽  
Design Environment ◽  
Surface Potentials ◽  
Graphene Field Effect Transistor ◽  
Dual Gate ◽  
Effect Transistor

In this work, a surface potential modeling approach has been proposed to model dual gate, bilayer graphene field effect transistor. The equivalent capacitive network of GFET has been improved considering the quantum capacitance effect for each layer and interlayer capacitances. Surface potentials of both layers are determined analytically from equivalent capacitive network. The explicit expression of drain to source current is established from drift-diffusion transport mechanism using the surface potentials of the layers. The drain current characteristics and transfer characteristics of the developed model shows good agreement with the experimental results in literatures. The small signal parameters of intrinsic graphene transistor i.e., output conductance ([Formula: see text]), transconductance ([Formula: see text]), gate to drain capacitance ([Formula: see text]) and gate to source capacitance ([Formula: see text]) have been derived and finally, the cut-off frequency is determined for the developed model. The model is compared with reported experimental data using Normalized Root Mean Square Error (NRMSE) metric and it shows less than [Formula: see text] NRMSE. A Verilog-A code has been developed for this model and a single ended frequency doubler has been designed in Cadence Design environment using this Verilog-A model.

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