Random-Access Multilevel Storage in Phase Change Memory by Staircase-Like Pulse Programming

2011 ◽  
Vol 497 ◽  
pp. 111-115
Author(s):  
Ryota Kobayashi ◽  
Tomoyuki Noguchi ◽  
You Yin ◽  
Sumio Hosaka
Keyword(s):  
Phase Change ◽  
Phase Change Memory ◽  
Random Access ◽  
Experimental Results ◽  
Device Resistance ◽  
Multilevel Storage ◽  
Simulation Results ◽  
Change Memory

We have investigated random-access multilevel storage in phase change memory by staircase-like pulse programming. Staircase-like pulse consists of first sub-pulse and second sub-pulse. Our simulation exhibited that any resistance levels are expected to be randomly accessed by controlling the crystallization with different widths of second sub-pulset2. Based on the simulation results, we did experiment on staircase-like pulse programming. Experimental results showed that the device resistance gradually increased with reducing second sub-pulset2to 0 ns. In other words, random access to any resistance levels was demonstrated to be possible simply by changingt2.

Simulation and Design of a Silicon Nanowire based Phase Change Memory Cell

2012 ◽  
Vol 1431 ◽  
Author(s):  
Ramin Banan Sadeghian ◽  
Yusuf Leblebici ◽  
Ali Shakouri
Keyword(s):  
Phase Change ◽  
High Speed ◽  
Low Cost ◽  
Silicon Nanowire ◽  
Phase Change Memory ◽  
Random Access ◽  
Memory Cell ◽  
Oxide Thickness ◽  
Nanowire Diameter ◽  
Change Memory

ABSTRACTIn this work we present preliminary calculations and simulations to demonstrate feasibility of programming a nanoscale Phase Change Random Access Memory (PCRAM) cell by means of a silicon nanowire ballistic transistor (SNWBT). Memory cells based on ballistic transistors bear the advantage of having a small size and high-speed operation with low power requirements. A one-dimensional MOSFET model (FETToy) was used to estimate the output current of the nanowire as a function of its diameter. The gate oxide thickness was 1.5 nm, and the Fermi level at source was set to -0.32 eV. For the case of VDS = VGS = 1 V, when the nanowire diameter was increased from 1 to 60 nm, the output power density dropped from 109 to 106 W cm-2 , while the current increased from 20 to 90 μA. Finite element electro-thermal analysis were carried out on a segmented cylindrical phase-change memory cell made of Ge2Sb2Te5 (GST) chalcogenide, connected in series to the SNWBT. The diameter of the combined device, d, and the aspect ratio of the GST region were selected so as to achieve optimum heating of the GST. With the assumption that the bulk thermal conductivity of GST does not change significantly at the nanoscale, it was shown that for d = 24 nm, a ‘reset’ programming current of ID = 80 μA can heat the GST up to its melting point. The results presented herein can help in the design of low cost, high speed, and radiation tolerant nanoscale PCRAM devices.

scholarly journals R-Tree for phase change memory

2017 ◽  
Vol 14 (2) ◽  
pp. 347-367 ◽  
Author(s):  
Elkhan Jabarov ◽  
Byung-Won On ◽  
Gyu Choi ◽  
Myong-Soon Park
Keyword(s):  
Phase Change ◽  
Spatial Data ◽  
Processing Time ◽  
Fill Factor ◽  
Phase Change Memory ◽  
Experimental Results ◽  
Location Information ◽  
Node Size ◽  
Blank Node ◽  
Change Memory

Nowadays, many applications use spatial data for instance-location information, so storing spatial data is important.We suggest using R -Tree over PCM. Our objective is to design a PCM-sensitive R -Tree that can store spatial data as well as improve the endurance problem. Initially, we examine how R -Tree causes endurance problems in PCM, and we then optimize it for PCM. We propose doubling the leaf node size, writing a split node to a blank node, updating parent nodes only once and not merging the nodes after deletion when the minimum fill factor requirement does not meet. Based on our experimental results while using benchmark dataset, the number of write operations to PCM in average decreased by 56 times by using the proposed R -Tree. Moreover, the proposed R -Tree scheme improves the performance in terms of processing time in average 23% compared to R -Tree.

Ultra-Multilevel-Storage Phase Change Memory

2014 ◽  
Vol 936 ◽  
pp. 599-602
Author(s):  
You Yin ◽  
Sumio Hosaka
Keyword(s):  
Phase Change ◽  
Phase Change Memory ◽  
Single Layer ◽  
Programming Method ◽  
Promising Method ◽  
Device Structure ◽  
Material Engineering ◽  
Structure Reliability ◽  
Multilevel Storage ◽  
Change Memory

In this study, we investigated ultra-multilevel-storage (UMLS) in lateral phase change memory (PCM) on the basis of device structure, reliability and programming method. We found that the number of resistance levels was limited strictly by the number of PC layers in multilayer multilevel cell (ML-MLC). A number of distinct levels up to 16 were obtained using a simple single-layer multilevel cell (SL-MLC). And material engineering is expected to greatly improve the reliability of MLS. We believe that fast-freely-achievable (FFA)-MLC by stair-like-pulse programming is a very promising method for futures application.

Effect of a separate heater structure for crystallisation to enable multilevel storage phase-change memory

2014 ◽  
Vol 11 (5/6/7/8) ◽  
pp. 389
Author(s):  
Rosalena Irma Alip ◽  
Zulfakri Mohamad ◽  
You Yin ◽  
Sumio Hosaka
Keyword(s):  
Phase Change ◽  
Phase Change Memory ◽  
Multilevel Storage ◽  
Change Memory

Multilevel Storage in Lateral Top-Heater Phase-Change Memory

2008 ◽  
Vol 29 (8) ◽  
pp. 876-878 ◽  
Author(s):  
You Yin ◽  
Kazuhiro Ota ◽  
Naoya Higano ◽  
Hayato Sone ◽  
Sumio Hosaka
Keyword(s):  
Phase Change ◽  
Phase Change Memory ◽  
Multilevel Storage ◽  
Change Memory

Thermal analysis of nonvolatile and non rotation phase change memory cell

2003 ◽  
Vol 803 ◽  
Author(s):  
L. P. Shi ◽  
T. C. Chong ◽  
J. M. Li ◽  
H. X. Yang ◽  
J. Q. Mou
Keyword(s):  
Phase Change ◽  
Electric Pulse ◽  
Phase Change Memory ◽  
Three Dimensional ◽  
Flow Characteristics ◽  
Random Access ◽  
Current Density Distribution ◽  
Memory Cell ◽  
Temperature History ◽  
Change Memory

ABSTRACTIn this paper, a three-dimensional finite-element modeling is performed for the analyses of Chalcogenide Random Access Memory (C-RAM), a non-rotation nonvolatile phase change memory cell. The thermal effect generated by an incident electric pulse was mainly discussed. Thermal performances of the cell as a result of electrical and geometrical variations were quantified. Current density distribution, temperature profiles, temperature history, heating rate, cooling rate, and heat flow characteristics were obtained and analyzed. The study is useful for the failure analysis of the C-RAM.

scholarly journals Error-Vulnerable Pattern-Aware Binary-to-Ternary Data Mapping for Improving Storage Density of 3LC Phase Change Memory

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 626
Author(s):  
Jeong Beom Hong ◽  
Young Sik Lee ◽  
Yong Wook Kim ◽  
Tae Hee Han
Keyword(s):  
Phase Change ◽  
Phase Change Memory ◽  
Random Access ◽  
Main Memory ◽  
Data Mapping ◽  
Storage Density ◽  
Ternary Data ◽  
And Performance ◽  
Parallel Encoding ◽  
Change Memory

Multi-level cell (MLC) phase-change memory (PCM) is an attractive solution for next-generation memory that is composed of resistance-based nonvolatile devices. MLC PCM is superior to dynamic random-access memory (DRAM) with regard to scalability and leakage power. Therefore, various studies have focused on the feasibility of MLC PCM-based main memory. The key challenges in replacing DRAM with MLC PCM are low reliability, limited lifetime, and long write latency, which are predominantly affected by the most error-vulnerable data pattern. Based on the physical characteristics of the PCM, where the reliability depends on the data pattern, a tri-level-cell (3LC) PCM has significantly higher performance and lifetime than a four-level-cell (4LC) PCM. However, a storage density is limited by binary-to-ternary data mapping. This paper introduces error-vulnerable pattern-aware binary-to-ternary data mapping utilizing 3LC PCM without an error-correction code (ECC) to enhance the storage density. To mitigate the storage density loss caused by the 3LC PCM, a two-way encoding is applied. The performance degradation is minimized through parallel encoding. The experimental results demonstrate that the proposed method improves the storage density by 17.9%. Additionally, the lifetime and performance are enhanced by 36.1% and 38.8%, respectively, compared with those of a 4LC PCM with an ECC.

ИССЛЕДОВАНИЕ ЭФФЕКТА ПЕРЕКЛЮЧЕНИЯ И ТРАНСПОРТА ЗАРЯДА В БЕСФОРМОВОЧНОМ МЕМРИСТОРЕ НА ОСНОВЕ НИТРИДА КРЕМНИЯ С РАЗНЫМИ ТИПАМИ МЕТАЛЛА ВЕРХНЕГО ЭЛЕКТРОДА, "Электронная техника. Серия 3. Микроэлектроника"

2020 ◽  
pp. 42-46
Author(s):  
Г.Я. Красников ◽  
О.М. Орлов ◽  
В.В. Макеев
Keyword(s):  
Phase Change ◽  
Phase Change Memory ◽  
Random Access ◽  
Random Access Memory ◽  
Resistive Random Access Memory ◽  
Access Memory ◽  
Magnetoresistive Random Access Memory ◽  
Ferroelectric Memories ◽  
Change Memory

Мемристорная резистивная память с произвольным доступом (ReRAM, Resistive Random Access Memory) вместе с памятью с изменением фазового состояния (PCM, Phase Change Memory), магниторезистивной памятью с произвольным доступом (MRAM, Magnetoresistive Random Access Memory), сегнетоэлектрической памятью (FeRAM, Ferroelectric Memories) [4] являются востребованными видами энергонезависимой памяти на новых альтернативных принципах. Нитрид кремния является перспективным резистивным переключающим слоем для мемристоров. В данной работе проведено экспериментальное исследование эффекта переключения и переноса заряда в мемристоре на основе нитрида кремния для разных типов металла (Ni, Co, Cu) верхнего электрода.

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