Direct Observation of Dielectric Breakdown Spot in Thermal Oxides on 4H-SiC(0001) Using Conductive Atomic Force Microscopy

2010 ◽  
Vol 645-648 ◽  
pp. 821-824 ◽  
Author(s):  
Kohei Kozono ◽  
Takuji Hosoi ◽  
Yusuke Kagei ◽  
Takashi Kirino ◽  
Shuhei Mitani ◽  
...  

The dielectric breakdown mechanism in 4H-SiC metal-oxide-semiconductor (MOS) devices was studied using conductive atomic force microscopy (C-AFM). We performed time-dependent dielectric breakdown (TDDB) measurements using a line scan mode of C-AFM, which can characterize nanoscale degradation of dielectrics. It was found that the Weibull slope () of time-to-breakdown (tBD) statistics in 7-nm-thick thermal oxides on SiC substrates was much larger for the C-AFM line scan than for the common constant voltage stress TDDB tests on MOS capacitors, suggesting the presence of some weak spots in the oxides. Superposition of simultaneously obtained C-AFM topographic and current map images of SiO2/SiC structure clearly demonstrated that most of breakdown spots were located at step bunching. These results indicate that preferential breakdown at step bunching due to local electric field concentration is the probable cause of poor gate oxide reliability of 4H-SiC MOS devices.

2007 ◽  
Vol 556-557 ◽  
pp. 501-504 ◽  
Author(s):  
Patrick Fiorenza ◽  
Raffaella Lo Nigro ◽  
Vito Raineri ◽  
Dario Salinas

The nano-characterization of thermal oxides grown on 4H-SiC is for the first time presented and analysed to derive its reliability. The dielectric breakdown (BD) kinetics of silicon dioxide (SiO2) thin films thermally grown on 4H-SiC has been determined by comparison between I-V measurements on large-area (up to 1.96×10-5 cm2) metal-oxide-semiconductor (MOS) structures and conductive atomic force microscopy (C-AFM) with a resolution of a few nanometers. C-AFM clearly images the weak breakdown single spots under constant voltage stresses. The stress time on the single C-AFM tip dot has been varied from 1×10-3 to 1×10-1 s. The density of BD spots, upon increasing the stress time, exhibits an exponential trend. The Weibull slope and the characteristic time of the dielectric BD events were so determined by direct measurements at nanometer scale demonstrating that the percolation model is valid for thin thermal oxide layers on 4H-SiC (5-7nm), but it fails for larger thicknesses (10 nm).


Author(s):  
Werner Frammelsberger ◽  
Guenther Benstetter ◽  
Thomas Schweinboeck ◽  
Richard Stamp ◽  
Janice Kiely

Abstract In this work a procedure is presented to look beneath the surface of a SiO2 film and to study the impact of the SiO2/Si interface morphology on the tunneling current, with high lateral resolution, by use of combined Conductive Atomic Force Microscopy (C-AFM) and Intermittent-Contact AFM (IC-AFM) measurements. Evidence is given that interface structures do have direct influence on the distribution of high current spots in MOS capacitors.


2011 ◽  
Vol 98 (9) ◽  
pp. 092902 ◽  
Author(s):  
K. Ganesan ◽  
S. Ilango ◽  
S. Mariyappan ◽  
M. Farrokh Baroughi ◽  
M. Kamruddin ◽  
...  

Author(s):  
Lucile C. Teague Sheridan ◽  
Linda Conohan ◽  
Chong Khiam Oh

Abstract Atomic force microscopy (AFM) methods have provided a wealth of knowledge into the topographic, electrical, mechanical, magnetic, and electrochemical properties of surfaces and materials at the micro- and nanoscale over the last several decades. More specifically, the application of conductive AFM (CAFM) techniques for failure analysis can provide a simultaneous view of the conductivity and topographic properties of the patterned features. As CMOS technology progresses to smaller and smaller devices, the benefits of CAFM techniques have become apparent [1-3]. Herein, we review several cases in which CAFM has been utilized as a fault-isolation technique to detect middle of line (MOL) and front end of line (FEOL) buried defects in 20nm technologies and beyond.


Author(s):  
Jon C. Lee ◽  
J. H. Chuang

Abstract As integrated circuits (IC) have become more complicated with device features shrinking into the deep sub-micron range, so the challenge of defect isolation has become more difficult. Many failure analysis (FA) techniques using optical/electron beam and scanning probe microscopy (SPM) have been developed to improve the capability of defect isolation. SPM provides topographic imaging coupled with a variety of material characterization information such as thermal, magnetic, electric, capacitance, resistance and current with nano-meter scale resolution. Conductive atomic force microscopy (C-AFM) has been widely used for electrical characterization of dielectric film and gate oxide integrity (GOI). In this work, C-AFM has been successfully employed to isolate defects in the contact level and to discriminate various contact types. The current mapping of C-AFM has the potential to identify micro-leaky contacts better than voltage contrast (VC) imaging in SEM. It also provides I/V information that is helpful to diagnose the failure mechanism by comparing I/V curves of different contact types. C-AFM is able to localize faulty contacts with pico-amp current range and to characterize failure with nano-meter scale lateral resolution. C-AFM should become an important technique for IC fault localization. FA examples of this technique will be discussed in the article.


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