Two-Way Tunneling Model of Oxide Trap Charging and Discharging in SiC MOSFETs

2012 ◽  
Vol 717-720 ◽  
pp. 465-468 ◽  
Author(s):  
Aivars J. Lelis ◽  
Daniel B. Habersat ◽  
Ronald Green ◽  
Neil Goldsman
Keyword(s):  
Threshold Voltage ◽  
Experimental Results ◽  
Measurement Time ◽  
Tunneling Model ◽  
Bias Stress ◽  
Voltage Instability ◽  
Oxide Trap

A two-way tunneling model describing simultaneous oxide trap charging and discharging in SiC MOSFETs is presented, along with a comparison with experimental results. This model can successfully account for the variation in threshold-voltage instability observed as a function of bias-stress time, bias-stress magnitude, and measurement time.

Research on Threshold Voltage Instability in SiC MOSFET Devices with Precision Measurement

2019 ◽  
Vol 954 ◽  
pp. 133-138
Author(s):  
Ao Liu ◽  
Song Bai ◽  
Run Hua Huang ◽  
Tong Tong Yang ◽  
Hao Liu
Keyword(s):  
Threshold Voltage ◽  
Precision Measurement ◽  
Gate Dielectric ◽  
Interface Traps ◽  
Gate Bias ◽  
Threshold Voltage Shift ◽  
Experimental Platform ◽  
Bias Stress ◽  
Voltage Instability ◽  
Voltage Drift

The mechanism of threshold voltage shift was studied. It is believed that the instability in threshold voltage during gate bias stress is due to capture of electrons by the SiC/gate dielectric interface traps and the gate dielectric near interface traps. New experimental platform was designed and built successfully. When positive stress or negative stress is applied to the gate, the change of threshold voltage occur immediately. After stress removal, the recovery of the threshold voltage occur soon. The change and recovery of threshold voltage are very sensitive to time. In order to get accurate threshold voltage drift data after high-temperature gate bias experiment, test of threshold voltage must be carried out immediately after the experiment.

Threshold-Voltage Instability in SiC MOSFETs Due to Near-Interfacial Oxide Traps

2016 ◽  
Vol 858 ◽  
pp. 585-590 ◽  
Author(s):  
Aivars J. Lelis ◽  
Ronald Green ◽  
Daniel B. Habersat
Keyword(s):  
Threshold Voltage ◽  
Charge Trapping ◽  
Test Methods ◽  
Device Failure ◽  
Voltage Instability ◽  
Oxide Trap ◽  
Oxide Traps ◽  
Trap Activation

There are two basic mechanisms that affect the threshold-voltage (VT) stability: oxide-trap activation and oxide-trap charging. Once additional oxide traps are activated, then they are free to participate in the charge-trapping processes that can, especially for older vintage devices, result in large VT shifts and potential device failure. More recent commercially-available devices show much smaller effects, and minimal trap activation. Given the dramatic improvements, it is now imperative that improved test methods be employed to properly separate out bad devices from good devices.

Time Dependence of Bias-Stress-Induced SiC MOSFET Threshold-Voltage Instability Measurements

2008 ◽  
Vol 55 (8) ◽  
pp. 1835-1840 ◽  
Author(s):  
Aivars J. Lelis ◽  
Daniel Habersat ◽  
Ronald Green ◽  
Aderinto Ogunniyi ◽  
Moshe Gurfinkel ◽  
...  
Keyword(s):  
Time Dependence ◽  
Threshold Voltage ◽  
Bias Stress ◽  
Voltage Instability

Bias Stress-Induced Threshold-Voltage Instability of SiC MOSFETs

2006 ◽  
Vol 527-529 ◽  
pp. 1317-1320 ◽  
Author(s):  
Aivars J. Lelis ◽  
Daniel B. Habersat ◽  
G. Lopez ◽  
J.M. McGarrity ◽  
F. Barry McLean ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Room Temperature ◽  
Field Effect Transistors ◽  
Linear Increase ◽  
Oxide Semiconductor ◽  
Bias Stress ◽  
Voltage Instability ◽  
Current Voltage ◽  
Oxide Traps ◽  
Charge Tunneling

We have observed instability in the threshold voltage, VT, of SiC metal-oxide semiconductor field-effect transistors (MOSFETs) due to gate-bias stressing. This effect has routinely been observed by us in all 4H and 6H SiC MOSFETs from three different manufacturers—even at room temperature. A positive-bias stress, applying an electric field of about 1 to 2 MV/cm across the gate oxide, for 3 minutes followed by a negative-bias stress for another 3 minutes typically results in a shift of the ID-VGS current-voltage characteristic in the range of 0.25 to 0.5 V and is repeatable. We speculate that this effect is due to the presence of a large number of near-interfacial oxide traps that presumably lie in the oxide transition region that extends several nm into the oxide from the SiC interface, caused by the presence of C and strained SiO2. This instability is consistent with charge tunneling in and out of these near-interfacial oxide traps, which in irradiated Si MOSFETs has been attributed to border traps. Also consistent with charge tunneling is the observed linear increase in the magnitude of the SiC VT instability with log (time).

Bias Stress-Induced Threshold-Voltage Instability of SiC MOSFETs

2006 ◽  
pp. 1317-1320 ◽  
Author(s):  
Aivars J. Lelis ◽  
D.B. Habersat ◽  
G. Lopez ◽  
J.M. McGarrity ◽  
F. Barry McLean ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Bias Stress ◽  
Voltage Instability

The Effect of Dynamic Bias Stress on the Photon-Enhanced Threshold Voltage Instability of Amorphous HfInZnO Thin-Film Transistors

2011 ◽  
Vol 32 (2) ◽  
pp. 164-166 ◽  
Author(s):  
Kyoung-Seok Son ◽  
Hyun-Suk Kim ◽  
Wan-Joo Maeng ◽  
Ji-Sim Jung ◽  
Kwang-Hee Lee ◽  
...  
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Bias Stress ◽  
Voltage Instability ◽  
Dynamic Bias

Investigation of threshold voltage instability induced by gate bias stress in ZnO nanowire field effect transistors

2012 ◽  
Vol 23 (48) ◽  
pp. 485201 ◽  
Author(s):  
Minhyeok Choe ◽  
Woojin Park ◽  
Jang-Won Kang ◽  
Sehee Jeong ◽  
Woong-Ki Hong ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Gate Bias ◽  
Zno Nanowire ◽  
Bias Stress ◽  
Voltage Instability ◽  
Gate Bias Stress

Effect of SiC Power DMOSFET Threshold-Voltage Instability

2008 ◽  
Vol 1069 ◽  
Author(s):  
Aivars Lelis ◽  
D. Habersat ◽  
R. Green ◽  
A. Ogunniyi ◽  
M. Gurfinkel ◽  
...  
Keyword(s):  
Leakage Current ◽  
Threshold Voltage ◽  
Power Loss ◽  
Gate Oxide ◽  
Primary Effect ◽  
Bias Stress ◽  
Voltage Instability ◽  
Oxide Traps ◽  
State Resistance

ABSTRACTWe have performed bias-stress induced threshold-voltage instability measurements on fully processed 4-H SiC power DMOSFETs as a function of bias-stress time, field, and temperature and have observed similar instabilities to those previously reported for lateral SiC MOSFET test structures. This effect is likely due to electrons tunneling into and out of near-interfacial oxide traps that extend spatially into the gate oxide. As long as the threshold voltage is set high enough to preclude the onset of subthreshold drain leakage current in the blocking state, then the primary effect of this instability is to increase the on-state resistance. For well-behaved power DMOSFETs, this would increase the power loss by no more than a few percent.

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