Bias-Temperature-Stress Response of Commercially-Available SiC Power MOSFETs

2015 ◽  
Vol 821-823 ◽  
pp. 677-680 ◽  
Author(s):  
Ronald Green ◽  
Aivars J. Lelis ◽  
Mooro El ◽  
Daniel B. Habersat
Keyword(s):  
Stress Response ◽  
Temperature Stress ◽  
Threshold Voltage ◽  
Stress Condition ◽  
Negative Bias ◽  
Gate Bias ◽  
Strong Function ◽  
Power Mosfets ◽  
Bias Temperature Stress ◽  
The Stability

The stability of the threshold voltage of commercial SiC MOSFETs from two device manufactures has been evaluated and compared when subject to positive and negative bias-temperature-stress conditions. For both device groupings, the worse-case stress occurred under negative bias temperature conditions with VGS = –15 V and a stress temperature of 200 °C. Devices in the Vendor A grouping exhibited acceleration in their bias-temperature-stress response that occurred earlier in time as a strong function of stress-temperature and to a lesser degree on gate-bias magnitude. Devices in the Vendor B grouping showed some evidence of acceleration, but only for the worse-case stress condition. Threshold voltage shifts for this device group were very low and extremely stable, with recorded values below 0.4 V for most conditions.

1700V, 5.5mOhm-cm2 4H-SiC DMOSFET with Stable 225°C Operation

2014 ◽  
Vol 778-780 ◽  
pp. 903-906 ◽  
Author(s):  
Kevin Matocha ◽  
Kiran Chatty ◽  
Sujit Banerjee ◽  
Larry B. Rowland
Keyword(s):  
High Temperature ◽  
Temperature Stress ◽  
High Temperatures ◽  
Threshold Voltage ◽  
Room Temperature ◽  
Gate Bias ◽  
Threshold Voltage Shift ◽  
Device Reliability ◽  
Bias Temperature Stress ◽  
High Temperature Operation

We report a 1700V, 5.5mΩ-cm24H-SiC DMOSFET capable of 225°C operation. The specific on-resistance of the DMOSFET designed for 1200V applications is 8.8mΩ-cm2at 225°C, an increase of only 60% compared to the room temperature value. The low specific on-resistance at high temperatures enables a smaller die size for high temperature operation. Under a negative gate bias temperature stress (BTS) at VGS=-15 V at 225°C for 20 minutes, the devices show a threshold voltage shift of ΔVTH=-0.25 V demonstrating one of the key device reliability requirements for high temperature operation.

Characterization of Threshold Voltage Shift by Negative Bias Temperature Stress in HfSiOx Films

2019 ◽  
Vol 19 (2) ◽  
pp. 393-402
Author(s):  
Chihiro Tamura ◽  
Tomohiro Hayashi ◽  
Yuuki Kikuchi ◽  
Kenji Ohmori ◽  
Ryu Hasunuma ◽  
...  
Keyword(s):  
Temperature Stress ◽  
Threshold Voltage ◽  
Negative Bias ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Bias Temperature Stress

Performance Enhancement of Channel-Engineered Al–Zn–Sn–O Thin-Film Transistors with Highly Conductive In–Ga–Zn–O Buried Layer via Vacuum Rapid Thermal Annealing

2020 ◽  
Vol 20 (8) ◽  
pp. 4671-4677
Author(s):  
Sung-Hun Kim ◽  
Won-Ju Cho
Keyword(s):  
Thin Film ◽  
Thermal Annealing ◽  
Temperature Stress ◽  
Rapid Thermal Annealing ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
High Performance ◽  
Gate Bias ◽  
Buried Layer ◽  
Bias Temperature Stress

In this study, we propose, fabricate, and examine the electrical characteristics of high-performance channel-engineered amorphous aluminum-doped zinc tin oxide (a-AZTO) thin-film transistors (TFTs). Amorphous indium gallium zinc oxide (a-IGZO) film with improved conductivity (obtained via rapid thermal annealing in vacuum) is applied as the local conductive buried layer (LCBL) of the channel-engineered a-AZTO TFTs. The optical transmittance of the a-IGZO and a-AZTO films in the visible region is >85%. The a-IGZO LCBL reduces the resistance of the a-AZTO channel, thereby resulting in increased drain current and improved device performance. We find that our fabricated channel-engineered a-AZTO TFTs with LCBLs are superior to non-channel-engineered a-AZTO TFTs without LCBLs in terms of electrical properties such as the threshold voltage, mobility, subthreshold swing, and on–off current ratios. In particular, as the a-IGZO LCBL length at the bottom of the channel increases, the channel resistance gradually decreases, eventually resulting in a mobility of 22.8 cm2/V · s, subthreshold swing of 470 mV/dec, and on–off current ratio of 3.98×107. We also investigate the effect of the a-IGZO LCBL on the operational reliability of a-AZTO TFTs by measuring the variation in the threshold voltage for positive gate bias temperature stress (PBTS), negative gate bias temperature stress (NBTS), and negative gate bias temperature illumination stress (NBTIS). The results indicate that the TFT instability for temperature and light is not affected by the LCBL. Therefore, our proposed channel-engineered a-AZTO TFT can form a promising high-performance high-reliability switching device for next-generation displays.

Threshold Voltage Instabilities of Present SiC-Power MOSFETs under Positive Bias Temperature Stress

2016 ◽  
Vol 858 ◽  
pp. 481-484 ◽  
Author(s):  
Gerald Rescher ◽  
Gregor Pobegen ◽  
Tibor Grasser
Keyword(s):  
Temperature Stress ◽  
Threshold Voltage ◽  
Physical Property ◽  
Oxide Thickness ◽  
Positive Bias ◽  
Threshold Voltage Shift ◽  
Power Mosfets ◽  
Fundamental Physical Property ◽  
Bias Temperature Stress ◽  
Silicon Based

We study the threshold voltage (Vth) instability of commercially available silicon carbide (SiC) power MOSFETs or prototypes from four different manufacturers under positive bias temperature stress (PBTS). A positive bias near the Vth causes a threshold voltage shift of 0.7 mV per decade in time per nanometer oxide thickness in the temperature range between-50 °C and 150 °C. Recovery at +5 V after a 100 s +25 V gate-pulse causes a recovery between-1.5 mV/dec/nm and-1.0 mV/dec/nm at room temperature and is decreasing with temperature. All devices show similar stress, recovery and temperature dependent behavior indicating that the observed Vth instabilities are likely a fundamental physical property of the SiC-SiO2 system caused by electron trapping in near interface traps. It is important to note that the trapping is not causing permanent damage to the interface like H-bond-breakage in silicon based devices and is nearly fully reversible via a negative gate bias.

Improved Burn-In Stress Methodology for Stress Uniformity

2018 ◽  
Author(s):  
Jungsuk Ko ◽  
Hoonchang yang ◽  
Hyungchae Jeon ◽  
Gyuyoung Nam ◽  
Youngseok Ryu ◽  
...  
Keyword(s):  
Temperature Stress ◽  
Stress Condition ◽  
Temperature Deviation ◽  
Stress Effects ◽  
Hot Temperature ◽  
Production Environments ◽  
Stress Environment ◽  
The Stability ◽  
Stress Uniformity ◽  
Stress Voltage

Abstract The necessity of hot temperature stress is widely recognized as the initial stress methodology to maintain the stability of products from infant defects in device [1, 2]. However, hot temperature stress has a disadvantage in terms of stress uniformity because temperature variation according to stress environment such as chamber, board, and tester accelerates different stress effects per chips. In addition, this stress condition can cause serious reliability problem in the mass production environments. Therefore, the stress temperature should be lowered to minimize the temperature deviation due to the production environments. The reduction of stress temperature cause the lack of stress amount, so optimized stress voltage and time to maintain the stress condition is required. In this study, various stress voltage and time with decreasing temperature were evaluated in consideration of lifetime that unit elements such transistors and capacitors did not degrade by any stress conditions. In addition, it was confirmed that stress uniformity can be improved in the stress condition obtained by the evaluation. Furthermore, the enhanced initial failure screen ability was proven with mass evaluations.

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