Dislocations Propagation Study Trough High-Resolution 4H-SiC Substrate Mapping

2019 ◽  
Vol 963 ◽  
pp. 276-279 ◽  
Author(s):  
Ruggero Anzalone ◽  
Nicolò Piluso ◽  
Andrea Severino ◽  
Simona Lorenti ◽  
Giuseppe Arena ◽  
...  
Keyword(s):  
High Resolution ◽  
Epitaxial Layer ◽  
Basal Plane ◽  
Stacking Faults ◽  
Screw Dislocations ◽  
Density Maps ◽  
Dislocations Density ◽  
Koh Etching

In this work a deep investigation of the dislocation on 4H-SiC substrate has been shown. The dislocation intersecting the surface were enhanced by KOH etching at 500 deg. C. performed on whole 6 inches substrate. A comparison between basal plane dislocations and threading screw dislocations in the substrate with the defects in the epitaxial layer (mainly stacking faults and carrots) was performed. The comparison between shows a correlation between basal plane dislocations density and stacking faults density maps.

New Separation Method of Threading Dislocations in 4H-SiC Epitaxial Layer by Molten KOH Etching

2011 ◽  
Vol 679-680 ◽  
pp. 298-301 ◽  
Author(s):  
T. Katsuno ◽  
Y. Watanabe ◽  
Fujiwara Hirokazu ◽  
Masaki Konishi ◽  
Takeo Yamamoto ◽  
...  
Keyword(s):  
Epitaxial Layer ◽  
Basal Plane ◽  
Separation Method ◽  
New Method ◽  
Threading Dislocations ◽  
Screw Dislocations ◽  
Etch Pit ◽  
Almost All ◽  
Edge Dislocations ◽  
Koh Etching

A new method for the separation of threading screw dislocations (TSD) and threading edge dislocations (TED) in a 4H-SiC epitaxial layer is proposed by measurement of the etch pit angles. The etch pit angles of the TSDs and TEDs were 28±3 and 18±3°, respectively. In the case of etch pit depths within the epitaxial layer, the values were almost constant. Almost all of the TSDs were converted from basal plane dislocations (BPDs) at the epitaxial layer/substrate interface.

Expansion of Stacking Faults in 4H-SiC Epitaxial Layer under Laser Light Excitation during Room Temperature Photoluminescence Mapping

2008 ◽  
Vol 600-603 ◽  
pp. 349-352 ◽  
Author(s):  
Norihiro Hoshino ◽  
Michio Tajima ◽  
M. Naitoh ◽  
Eiichi Okuno ◽  
Shoichi Onda
Keyword(s):  
Laser Beam ◽  
Epitaxial Layer ◽  
Basal Plane ◽  
High Intensity ◽  
Room Temperature ◽  
Stacking Faults ◽  
Scanning Laser ◽  
Epitaxial Layers ◽  
Dislocation Loops ◽  
Room Temperature Photoluminescence

We investigated the expansion of single Shockley stacking faults (SSFs) in a 4H-SiC epitaxial layer under high-intensity scanning laser beam during room temperature photoluminescence mapping, which is similar to the degradation of bipolar pin diodes during forward current injection. In an epitaxial layer on an 8 off-axis (0001) substrate, the SSF-related intensity patterns induced by scanning high-intensity laser beam were classified into two types. The first one was a triangular pattern and the second a pattern which expanded in accordance with the motion of the scanning laser beam. The origins of the SSFs responsible for both patterns are presumably due to the preexisting basal plane dislocations and the dislocation-loops on the basal plane in the epitaxial layer, respectively. On the other hand, most of the SSF-expansion in on-axis (11 2 0) epitaxial layers were similar to the second type in the (0001) epitaxial layer. We, therefore, suggest that the dislocation-loops, which were located close to the surface, were dominant nucleation-sites of the SSFs in the (11 2 0) epitaxial layers.

Large-Area Mapping of Dislocations in 4H-SiC from Carbon-Face (000-1) by Using Vaporized KOH Etching near 1000 °C

2013 ◽  
Vol 740-742 ◽  
pp. 829-832
Author(s):  
Yong Zhao Yao ◽  
Yukari Ishikawa ◽  
Koji Sato ◽  
Yoshihiro Sugawara ◽  
Katsunori Danno ◽  
...  
Keyword(s):  
Basal Plane ◽  
Chemical Etching ◽  
Sample Thickness ◽  
Large Area ◽  
Inexpensive Method ◽  
Etching Technique ◽  
Screw Dislocations ◽  
Wafer Thickness ◽  
Edge Dislocations ◽  
Koh Etching

To solve the problem that no preferential chemical etching is available for dislocation revelation from the carbon-face (C-face) of 4H-SiC, a novel etching technique using vaporized KOH has been developed. It was found that this etching technique can reveal the three commonly found dislocation types, i.e., threading screw dislocations (TSDs), threading edge dislocations (TEDs) and basal plane dislocations (BPDs) as large hexagonal, small hexagonal and triangular, respectively. Centimeter-scale dislocation mapping has been obtained, and the pit positions on the C-face were compared with those on the Si-face, to study the dislocation propagation behaviors across the sample thickness. We have found one-to-one correlation for nearly 96% of the TSDs, indicating a dominant proportion of TSDs penetrate the whole wafer thickness. The vaporized KOH etching technique has provided an effective and inexpensive method of making inch-scale mapping of dislocation distribution for the C-face epitaxial and bulky 4H-SiC.

Dislocation Revelation in Highly Doped N-Type 4H-SiC by Molten KOH Etching with Na2O2 Additive

2011 ◽  
Vol 679-680 ◽  
pp. 290-293 ◽  
Author(s):  
Yong Zhao Yao ◽  
Yukari Ishikawa ◽  
Yoshihiro Sugawara ◽  
Hiroaki Saitoh ◽  
Katsunori Danno ◽  
...  
Keyword(s):  
Electron Concentration ◽  
Basal Plane ◽  
Wet Etching ◽  
Etch Pits ◽  
Screw Dislocations ◽  
Edge Dislocations ◽  
Koh Etching

We have proposed a new wet etching recipe using molten KOH and Na2O2 as the etchant (“KN etching”) for dislocation revelation in highly doped n-type 4H-SiC (n+-4H-SiC). Threading screw dislocations (TSDs) and threading edge dislocations (TEDs) have been clearly revealed as hexagonal etch pits differing in pit sizes, and basal plane dislocations (BPDs) as seashell-shaped pits. This new etching recipe has provided a solution to the problem that conventional KOH etching is not effective for dislocation identification in 4H-SiC if the electron concentration is high (>mid-1018 cm-3). We have investigated the effect of SiC off-cut angle on KN etching and it has been shown that the “KN etching” is applicable for the n+-SiC substrate with off-angle from 0o to 8o.

Characterization of Basal Plane Dislocations in 4H-SiC Substrates by Topography Analysis of Threading Edge Dislocations in Epilayers

2010 ◽  
Vol 645-648 ◽  
pp. 303-306 ◽  
Author(s):  
Isaho Kamata ◽  
Masahiro Nagano ◽  
Hidekazu Tsuchida
Keyword(s):  
High Resolution ◽  
Epitaxial Layer ◽  
Basal Plane ◽  
Grazing Incidence ◽  
Size Difference ◽  
Etch Pits ◽  
Burgers Vector ◽  
Vector Direction ◽  
Edge Dislocations

Burgers vector directions of threading edge dislocations (TEDs) in 4H-SiC epitaxial layer are distinguished by grazing incidence high resolution topography. Based on comparison between appearance of KOH etch pits and direction of TED Burgers vector, the size difference of the TED etch pits is found to be dependent on their Burgers vector directions. Examining TEDs in the epilayer by topography, the Burgers vector direction of basal plane dislocations (BPDs) in the substrate is identified. Correspondence between the topography contrast and the sense of a BPD is also investigated.

Starting Point of Step-Bunching Defects on 4H-SiC Si-Face Substrates

2015 ◽  
Vol 821-823 ◽  
pp. 367-370 ◽  
Author(s):  
Kentaro Tamura ◽  
Masayuki Sasaki ◽  
Chiaki Kudou ◽  
Tamotsu Yamashita ◽  
Hideki Sako ◽  
...  
Keyword(s):  
Oxide Layer ◽  
Epitaxial Layer ◽  
Basal Plane ◽  
X Ray ◽  
Step Bunching ◽  
Line Feature ◽  
Starting Point ◽  
Basal Plane Dislocation ◽  
Koh Etching

On 4H-SiC Si-face substrates after H2etching, the defect with “line” feature parallel to a step as “bunched-step line” was observed. Using X-ray topography and KOH etching, we confirmed that the bunched-step line originated from basal plane dislocation (BPD). Use of the substrate with the lowest BPD density will be effective to reduce bunched-step line that would affect oxide layer reliability on an epitaxial layer. However, more detail investigation needs to classify the BPD that would become a starting point of bunched-step line.

VF Degradation of 4H-SiC PiN Diodes Using Low-BPD Wafers

2014 ◽  
Vol 778-780 ◽  
pp. 851-854 ◽  
Author(s):  
Chiharu Ota ◽  
Johji Nishio ◽  
Kazuto Takao ◽  
Takashi Shinohe
Keyword(s):  
Basal Plane ◽  
Stacking Faults ◽  
Optical Observation ◽  
Etch Pits ◽  
Pin Diodes ◽  
Bipolar Devices ◽  
Basal Plane Dislocation ◽  
Pl Mapping ◽  
Koh Etching ◽  
Free Area

In this paper, we found origin of VFdegradation of SiC bipolar devices other than a basal plane dislocation (BPD) in the SiC substrate. A VFdegradation of the 4H-SiC PiN diodes with low-BPD wafers was evaluated and its origins were discussed. Some diodes suffered VFdegradation, even though they were fabricated on BPD-free area. PL mapping, TEM image, and optical observation after KOH etching showed that there were Shockley stacking faults and combined etch-pits arrays, which were presumed to be caused by the device process.

Interaction of 6H-Type Stacking Faults with Threading Screw Dislocations in PVT-Grown 4H-SiC Single Crystals

2012 ◽  
Vol 717-720 ◽  
pp. 411-414
Author(s):  
Shinya Sato ◽  
T. Fujimoto ◽  
H. Tsuge ◽  
M. Katsuno ◽  
W. Ohashi
Keyword(s):  
High Resolution ◽  
Single Crystals ◽  
Room Temperature ◽  
Stacking Faults ◽  
Screw Dislocations ◽  
X Ray

6H-type stacking faults (SFs) observed in PVT-grown 4H-SiC ingle crystals were investigated using Photoluminescence (PL) microscopy at room temperature. Structural analyses using high resolution X-ray topography have revealed that there exist no (n=4, 8) component in Burger’s vectors of the 6H-type SFs we observed, strongly suggesting that the 6H-type SFs are constructed either by insertions of very thin 6H-type foreign polytype inclusions or by successive repetitions of Shockley-type in-plane glides.

Development of Non-Destructive In-House Observation Techniques for Dislocations and Stacking Faults in SiC Epilayers

2006 ◽  
Vol 527-529 ◽  
pp. 415-418 ◽  
Author(s):  
Isaho Kamata ◽  
Hidekazu Tsuchida ◽  
Toshiyuki Miyanagi ◽  
Tomonori Nakamura
Keyword(s):  
High Resolution ◽  
Stacking Faults ◽  
X Ray ◽  
Measurement Results ◽  
Pl Mapping ◽  
Synchotron Radiation ◽  
Non Destructive ◽  
Evaluation Techniques ◽  
Koh Etching ◽  
Low Temperature Photoluminescence

We have developed non-destructive in-house observation techniques for dislocations and stacking faults (SFs) in 4H-SiC epilayers. Low temperature photoluminescence (PL) mapping was carried out at 100K using He-Cd laser (325 nm) as an exciation source. PL mapping at ~420 nm was used to investigate basal plane dislocations (BPDs), Shockley stacking faults (SSFs) and boundary, while PL mapping at ~470 nm and 100K obtained in-grown SF images. In addition, using a high-resolution laboratory X-ray topography system with a four-crystal collimator, we succeeded in recording BPDs propagating along [11-20]. From the measurement results, new evaluation techniques for dislocations and SFs other than KOH etching and Synchotron radiation topography were demonstrated on Si- and C-face 4H-SiC epilayers.

Micropipe Dissociation through Thick n+ Buffer Layer Growth

2008 ◽  
Vol 600-603 ◽  
pp. 167-170
Author(s):  
Mike F. MacMillan ◽  
Edward K. Sanchez ◽  
Michael Dudley ◽  
Yi Chen ◽  
Mark J. Loboda
Keyword(s):  
Epitaxial Layer ◽  
Grazing Incidence ◽  
System Optimization ◽  
Layer Growth ◽  
Cross Sectional ◽  
Screw Dislocations ◽  
X Ray ◽  
Density Reduction ◽  
Wafer Surfaces ◽  
Koh Etching

Thick (> 25 µm) 4H n+ epitaxial layer growth was performed on 4H n+ substrates utilizing chlorine containing etch chemistries in a hot wall CVD system. Optimization of the n+ epitaxial layer growth was achieved by varying C/Si ratio and N2 flow. Desired epitaxial layers have doping levels > 5x1018 cm-3, epitaxial surface roughness <10 nm on a 20x20 µm area and overall micropipe density reduction. To confirm the conversion of micropipes into closed core screw dislocations, microscopic examination of the epitaxial and wafer surfaces was carried out after KOH etching. Grazing incidence x-ray topography (XRT) as well as cross sectional XRT and microscopy were also performed. The cross sectional evaluation showed that the dissociation of the micropipes occurs very close to the epitaxy/wafer interface.

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