Backside Chippings Improvement through Wafer Dicing Parameter Optimization and Understanding the Anistropic Silicon Properties

Semiconductor Companies and Industries soar high as the trend for electronic gadgets and devices increases. Transition from “manual” to “fully automatic” application is one of the advantages why consumer adapt to changes and prefer electronic devices as one of daily answers. Individuals who admire these electronic devices often ask how they are made. As we look inside each device, we can notice interconnected microchips commonly called IC (Integrated Circuit). These are specially prepared silicon wafers where integrated circuit are developed. Commonly, each device is composed of numerous microchips depending on the design and functionality IC production is processed from “front-end” to “back-end” assembly. Front-end assembly includes wafer fabrication where electrical circuitry is prepared and integrated to every single silicon wafers. Back-end assembly covers processing the wafer by cutting into smaller individual and independent components called “dice”. Each dice will be placed into Leadframe, bonded with wires prior encapsulating with mold compounds. After molding, each IC will be cut through a process called singulation. Afterwards, all molded units are subjected for functional testing. Dice is central to each IC; it is where miniature transistor, resistor and capacitor are integrated to form complex small circuitry in microchips. Pre-assembly (Pre-assy) stations have the first hand prior to all succeeding stations. Live wafers are primary direct materials processed in these stations. Robust work instruction and parameter must be practiced during handling and processing to avoid gross rejection and possible work-related defects. The paper is all about the challenges to resolve and improved the backside chippings in 280um wafer thickness in mechanical dicing saw. The conventional Mechanical dicing process induce a lot of mechanical stress and vibration during the cutting process which oftentimes lead to backside chipping and die crack issues. However, backside chippings can mitigate with proper selection of parameter settings and understand the silicon wafer properties.

Hybrid Bonding of Via-middle TSV Wafer Fabricated using Direct Si/Cu Grinding, Residual Metal Removal, CVD, and CMP

We performed hybrid bonding of a via-middle through-silicon via (TSV) wafer that was fabricated using direct Si/Cu grinding, residual metal removal, chemical vapor deposition of a rear-side insulator, and chemical mechanical polishing. The rear side of the via-middle TSV wafer (wafer diameter: 197 mm, wafer thickness: 22 μm, TSV diameter: 5.5 μm, and total thickness variation: <2 μm), which was mounted on a support glass, was bonded to a Cu electrode wafer (wafer diameter: 200 mm, wafer thickness: 625 μm, and Cu electrode diameter: 6 μm). The bonding was performed at room temperature via a surface-activated bonding using a Si ultrathin film. After hybrid bonding, the support glass was debonded, and vacuum annealing was performed. Cross-sectional observations and electrical measurements of the bonded samples were also performed. Both the SiO2–SiO2 interface and the TSV-Cu electrode interface were bonded by the Si ultrathin film. The measured resistance of the TSV-Cu electrode pair was low (approximately 0.12 Ω), and the leakage current between the TSV-Cu electrode pairs was low (1 pA at 5 V).

Achievement of Low Carrier Concentration of High-Uniformity SiC Films Grown by High Speed Wafer Rotation Vertical CVD Tool

N-type 4H-SiC homo-epitaxial films were grown by high speed wafer rotation vertical CVD tool, and effect of surface C/Si ratios on in-wafer uniformity and lower limit of carrier concentration of the SiC films on 150 mm diameter wafers was investigated. From analysis of in-wafer distribution by mapping of whole wafers, it was found that high in-wafer thickness uniformity was obtained for the films grown both at lower introduced C/Si ratio of about 1.35, which corresponds to surface C/Si ratio is lower than 1.0, and at higher introduced C/Si ratio of about 1.80, which corresponds to surface C/Si ratio is higher than 1.0. However, larger fluctuation of the carrier concentration at wafer edge was observed for the film grown at lower introduced C/Si ratio, compared with the film grown at higher introduced C/Si ratio. Lower fluctuation of the carrier concentration for the film grown at higher introduced C/Si ratio is thought to be due to lower sensitivity of carrier concentration on growth temperature, which is observed for the film grown at surface C/Si ratio higher than 1.0. Also, the film grown at higher introduced C/Si ratio showed longer carrier lifetime with higher uniformity, although the film grown at lower introduced C/Si ratio indicated shorter carrier lifetime with lower uniformity. The mean carrier concentration of the films grown at higher introduced C/Si ratio was reduced by two digits compared with those grown at lower introduced C/Si ratio, and low carrier concentration of 1.7 x 1014 cm-3 with high in-wafer uniformity for intentionally doped SiC film grown at higher introduced C/Si ratio was achieved. Based on the results mentioned above, fabrication of thick and low-doped epi layer on 150 mm diameter wafer with high in-wafer uniformity was demonstrated.

Improvement of Repeatability on N-Type 4H-SiC Epitaxial Growth by High Speed Wafer Rotation Vertical CVD Tool

N-type 4H-SiC homo-epitaxial films were grown on 150 mm diameter wafers by high speed wafer rotation vertical CVD tool, and effect of surface C/Si ratio on short-term and long-term repeatability of the SiC films was investigated. By tuning of growth condition, high uniform SiC film with in-wafer thickness uniformity of ±2.8 % (1.6 % σ/mean) and carrier concentration uniformity of ±3.1 % (1.9 % σ/mean) was successfully grown at higher introduced C/Si ratio of about 1.80, which corresponds to surface C/Si ratio higher than 1.0 on the whole wafer. This result was comparable to the film grown at lower introduced C/Si ratio of about 1.35, which corresponds to surface C/Si ratio lower than 1.0 on the whole wafer. On the other hand, the films on 13 wafers successively grown at higher introduced C/Si ratio indicated low fluctuation from 1.85 to 3.09 % (σ/mean), and the short-term repeatability of the in-wafer carrier concentration uniformity of the films grown at higher introduced C/Si ratio was improved compared with the films grown at lower introduced C/Si ratio. Additionally, in-wafer carrier concentration uniformity of the films on 171 wafers grown at higher introduced C/Si ratio showed 75 % quartile of 4.26 % (σ/mean), and this result was greatly superior to that of 8.21 % (σ/mean) for the films on 130 wafers grown at lower introduced C/Si ratio.

Laser-based Thickness Control in a Double-Side Polishing System for Silicon Wafers

Thickness control is a critical process of automated polishing of large and thin Si wafers in the semiconductor industry. In this paper, an elaborate double-side polishing (DSP) system is demonstrated, which has a polishing unit with feedback control of wafer thickness based on the scan data of a laser probe. Firstly, the mechanical structure, as well as the signal transmission and control of the DSP system, are discussed, in which the thickness feedback control is emphasized. Then, the precise positioning of the laser probe is explored to obtain the continuous and valid scan data of the wafer thickness. After that, a B-spline model is applied for the characterization of the wafer thickness function to provide the thickness control system with credible thickness deviation information. Finally, experiments of wafer-thickness evaluation and control are conducted on the presented DSP system. With the advisable number of control points in B-spline fitting, the thickness variation can be effectively controlled in wafer polishing with the DSP system, according to the experimental results of curve fitting and the statistical analysis of the experimental data.