Starting Point of Step-Bunching Defects on 4H-SiC Si-Face Substrates

2015 ◽  
Vol 821-823 ◽  
pp. 367-370 ◽  
Author(s):  
Kentaro Tamura ◽  
Masayuki Sasaki ◽  
Chiaki Kudou ◽  
Tamotsu Yamashita ◽  
Hideki Sako ◽  
...  
Keyword(s):  
Oxide Layer ◽  
Epitaxial Layer ◽  
Basal Plane ◽  
X Ray ◽  
Step Bunching ◽  
Line Feature ◽  
Starting Point ◽  
Basal Plane Dislocation ◽  
Koh Etching

On 4H-SiC Si-face substrates after H2etching, the defect with “line” feature parallel to a step as “bunched-step line” was observed. Using X-ray topography and KOH etching, we confirmed that the bunched-step line originated from basal plane dislocation (BPD). Use of the substrate with the lowest BPD density will be effective to reduce bunched-step line that would affect oxide layer reliability on an epitaxial layer. However, more detail investigation needs to classify the BPD that would become a starting point of bunched-step line.

scholarly journals Analysis of the Basal Plane Dislocation Density and Thermomechanical Stress during 100 mm PVT Growth of 4H-SiC

Materials ◽  
2019 ◽  
Vol 12 (13) ◽  
pp. 2207 ◽  
Author(s):  
Johannes Steiner ◽  
Melissa Roder ◽  
Binh Duong Nguyen ◽  
Stefan Sandfeld ◽  
Andreas Danilewsky ◽  
...  
Keyword(s):  
Basal Plane ◽  
Growth Parameters ◽  
Electronic Devices ◽  
Defect Distribution ◽  
Thermomechanical Stress ◽  
X Ray ◽  
Basal Plane Dislocation ◽  
The Impact ◽  
Koh Etching

Basal plane dislocations (BPDs) in 4H silicon carbide (SiC) crystals grown using the physical vapor transport (PVT) method are diminishing the performance of SiC-based power electronic devices such as pn-junction diodes or MOSFETs. Therefore, understanding the generation and movement of BPDs is crucial to grow SiC suitable for device manufacturing. In this paper, the impact of the cooldown step in PVT-growth on the defect distribution is investigated utilizing two similar SiC seeds and identical growth parameters except for a cooldown duration of 40 h and 70 h, respectively. The two resulting crystals were cut into wafers, which were characterized by birefringence imaging and KOH etching. The initial defect distribution of the seed wafer was characterized by synchrotron white beam X-ray topography (SWXRT) mapping. It was found that the BPD density increases with a prolonged cooldown time. Furthermore, small angle grain boundaries based on threading edge dislocation (TED) arrays, which are normally only inherited by the seed, were also generated in the case of the crystal cooled down in 70 h. The role of temperature gradients inside the crystal during growth and post-growth concerning the generation of shear stress is discussed and supported by numerical calculations.

Conversion of Basal Plane Dislocations to Threading Edge Dislocations in Growth of Epitaxial Layers on 4H-SiC Substrates with a Vicinal Off-Angle

2014 ◽  
Vol 778-780 ◽  
pp. 99-102 ◽  
Author(s):  
Keiko Masumoto ◽  
Sachiko Ito ◽  
Hideto Goto ◽  
Hirotaka Yamaguchi ◽  
Kentaro Tamura ◽  
...  
Keyword(s):  
Epitaxial Growth ◽  
Edge Dislocation ◽  
Basal Plane ◽  
Conversion Ratio ◽  
Epitaxial Layers ◽  
Etch Pits ◽  
X Ray ◽  
Basal Plane Dislocation ◽  
Edge Dislocations ◽  
Koh Etching

We have investigated a conversion of basal plane dislocation (BPD) to threading edge dislocation (TED) in growth of epitaxial layers (epi-layers) on 4H-SiC vicinal substrates with an off-angle of 0.85° at low C/Si ratio of 0.7 by using deep KOH etching and X-ray topography observations. Deep KOH etching indicated that BPDs in the substrates converted to TEDs in the epi-layers. X-ray topography observations suggested that the conversion occurred during epitaxial growth when the thickness of epi-layers was less than 1.5 μm. We found that the conversion ratio obtained from counting deep KOH etch pits was over 99%.

Evaluation of Basal Plane Dislocation Behavior in the Epitaxial Layer on a 4H-SiС Wafer Fabricated by the Solution Growth Method

2019 ◽  
Vol 963 ◽  
pp. 80-84 ◽  
Author(s):  
Kazuaki Seki ◽  
Kazuhiko Kusunoki ◽  
Shinsuke Harada ◽  
Toru Ujihara
Keyword(s):  
Epitaxial Layer ◽  
Basal Plane ◽  
Solution Method ◽  
Chemical Vapor ◽  
Bulk Crystals ◽  
Bipolar Devices ◽  
Basal Plane Dislocation ◽  
Growth Method ◽  
Dislocation Behavior ◽  
Koh Etching

A 4H-SiC 4° off-wafer fabricated from a bulk crystal grown using the solution method has high quality with extremely low-density threading screw (TSD) and basal plane (BPD) dislocations. For application to electronic devices, we formed an epitaxial layer on the solution-method-prepared wafer via chemical vapor deposition and evaluated the BPD in the epitaxial layer using synchrotron X-ray topography and molten KOH etching. The BPD density of the epitaxial layer formed on the solution-grown crystals was extremely low. Bulk crystals fabricated as wafers by the solution method are expected to be applied to high-voltage bipolar devices that do not suffer from degradation of forward characteristics.

Dislocations Propagation Study Trough High-Resolution 4H-SiC Substrate Mapping

2019 ◽  
Vol 963 ◽  
pp. 276-279 ◽  
Author(s):  
Ruggero Anzalone ◽  
Nicolò Piluso ◽  
Andrea Severino ◽  
Simona Lorenti ◽  
Giuseppe Arena ◽  
...  
Keyword(s):  
High Resolution ◽  
Epitaxial Layer ◽  
Basal Plane ◽  
Stacking Faults ◽  
Screw Dislocations ◽  
Density Maps ◽  
Dislocations Density ◽  
Koh Etching

In this work a deep investigation of the dislocation on 4H-SiC substrate has been shown. The dislocation intersecting the surface were enhanced by KOH etching at 500 deg. C. performed on whole 6 inches substrate. A comparison between basal plane dislocations and threading screw dislocations in the substrate with the defects in the epitaxial layer (mainly stacking faults and carrots) was performed. The comparison between shows a correlation between basal plane dislocations density and stacking faults density maps.

LPE Growth of Low Doped n-Type 4H-SiC Layer on On-Axis Substrate for Power Device Application

2009 ◽  
Vol 615-617 ◽  
pp. 141-144 ◽  
Author(s):  
Ryo Hattori ◽  
Kazuhito Kamei ◽  
Kazuhiko Kusunoki ◽  
Nobuyoshi Yashiro ◽  
S. Shimosaki
Keyword(s):  
Liquid Phase ◽  
Epitaxial Layer ◽  
Liquid Phase Epitaxy ◽  
Basal Plane ◽  
Power Device ◽  
Device Application ◽  
Basal Plane Dislocation ◽  
Low Nitrogen

LPE (liquid phase epitaxy) growth of low nitrogen unintentionally doped SiC epitaxial layer on on-axis 4H-SiC substrate using nitrogen getter Si based solution was investigated to realize basal plane dislocation (BPD) free epitaxial layer. A significant reduction in BPD was demonstrated.

Investigation of Basal Plane Dislocation Reduction/Elimination by Molten KOH-NaOH Eutectic Etching Method

2012 ◽  
Vol 717-720 ◽  
pp. 125-128 ◽  
Author(s):  
Hai Zheng Song ◽  
Tangali S. Sudarshan
Keyword(s):  
Epitaxial Growth ◽  
Basal Plane ◽  
Etch Pits ◽  
Etch Pit ◽  
Etching Method ◽  
Dislocation Reduction ◽  
Short Period ◽  
Basal Plane Dislocation ◽  
Non Destructive ◽  
Koh Etching

An optimized molten KOH-NaOH eutectic etching method is developed to reveal defects in highly n-doped SiC substrates and to pre-treat the substrate prior to epitaxial growth. Different from the conventional KOH etching method, by way of eutectic method, the basal plane dislocation (BPD) conversion in the subsequent epitaxial growth is independent of the etch pit size pre-generated on the substrate. Even with a short period (~3 minutes) of pretreatment which does not generate any visible etch pits or degradation of surface morphology on the substrate, an epilayer with low BPD density -2 is still achieved. This simple and non-destructive method shows high potential to be practically employed as one of the basic pretreatment steps to the substrates in SiC epitaxial growth in order to achieve very low or free BPD density.

VF Degradation of 4H-SiC PiN Diodes Using Low-BPD Wafers

2014 ◽  
Vol 778-780 ◽  
pp. 851-854 ◽  
Author(s):  
Chiharu Ota ◽  
Johji Nishio ◽  
Kazuto Takao ◽  
Takashi Shinohe
Keyword(s):  
Basal Plane ◽  
Stacking Faults ◽  
Optical Observation ◽  
Etch Pits ◽  
Pin Diodes ◽  
Bipolar Devices ◽  
Basal Plane Dislocation ◽  
Pl Mapping ◽  
Koh Etching ◽  
Free Area

In this paper, we found origin of VFdegradation of SiC bipolar devices other than a basal plane dislocation (BPD) in the SiC substrate. A VFdegradation of the 4H-SiC PiN diodes with low-BPD wafers was evaluated and its origins were discussed. Some diodes suffered VFdegradation, even though they were fabricated on BPD-free area. PL mapping, TEM image, and optical observation after KOH etching showed that there were Shockley stacking faults and combined etch-pits arrays, which were presumed to be caused by the device process.

Characterization and Reduction of Defects in 4H-SiC Substrate and Homo-Epitaxial Wafer

2020 ◽  
Vol 1004 ◽  
pp. 387-392 ◽  
Author(s):  
Long Yang ◽  
Li Xia Zhao ◽  
Hui Wang Wu ◽  
Yafei Liu ◽  
Tuerxun Ailihumaer ◽  
...  
Keyword(s):  
Basal Plane ◽  
Chemical Vapor ◽  
Vapor Transport ◽  
Etching Time ◽  
X Ray ◽  
Half Loop ◽  
Dislocation Behavior ◽  
Edge Dislocations ◽  
Defect Morphology ◽  
Koh Etching

4H-SiC substrates and homo-epitaxial layers were obtained using the traditional methods of physical vapor transport and chemical vapor deposition. Defect morphology has been studied using both Synchrotron White Beam X-ray Topography and Monochromatic Beam X-ray Topography. Molten KOH etching method was adopted to further investigate the dislocation behavior mechanisms. Deflected dislocations were observed at the periphery regions in both substrate and epitaxial wafers. 3C polytypes and half loop arrays were observed in the 4H-SiC epitaxial wafer. It is also found that the majority of basal plane dislocations are converted to threading edge dislocations in the epitaxial wafer samples. The proportion of BPD to TED conversion depends on the surface step morphology and growth mode in epitaxial growth which in turn depends on the C/Si ratio. By the optimization of etching time prior to epitaxy and C/Si ratio, high-quality epitaxial wafers with extremely low basal plane dislocations densities (＜0.1 cm-2) was obtained.

Characterization of 100 mm Diameter 4H-Silicon Carbide Crystals with Extremely Low Basal Plane Dislocation Density

2010 ◽  
Vol 645-648 ◽  
pp. 291-294 ◽  
Author(s):  
Michael Dudley ◽  
Ning Zhang ◽  
Yu Zhang ◽  
Balaji Raghothamachar ◽  
Sha Yan Byrapa ◽  
...  
Keyword(s):  
Silicon Carbide ◽  
Dislocation Density ◽  
Basal Plane ◽  
X Ray ◽  
Repetitive Process ◽  
Basal Plane Dislocation ◽  
And Behavior ◽  
New Generation ◽  
Edge Dislocations

Synchrotron White Beam X-ray Topography (SWBXT) studies are presented of basal plane dislocation (BPD) configurations and behavior in a new generation of 100mm diameter, 4H-SiC wafers with extremely low BPD densities (3-4 x 102 cm-2). The conversion of non-screw oriented, glissile BPDs into sessile threading edge dislocations (TEDs) is observed to provide pinning points for the operation of single ended Frank-Read sources. In some regions, once converted TEDs are observed to re-convert back into BPDs in a repetitive process which provides multiple BPD pinning points.

6.5 kV 4H-SiC PiN Diodes without Bipolar Degradation

2017 ◽  
Vol 897 ◽  
pp. 435-438 ◽  
Author(s):  
Yuan Bu ◽  
Hiroyuki Yoshimoto ◽  
Kumiko Konishi ◽  
Akio Shima ◽  
Yasuhiro Shimamoto
Keyword(s):  
Breakdown Voltage ◽  
Basal Plane ◽  
Room Temperature ◽  
Test Results ◽  
Leakage Currents ◽  
Pin Diodes ◽  
Basal Plane Dislocation ◽  
Koh Etching ◽  
A Current ◽  
Free Area

We designed, fabricated and evaluated 6.5 kV SiC PiN diodes. In order to suppress process-induced basal plane dislocation (BPD) in SiC PiN diodes, we improved the fabrication processes. The Ir-Vr measurements showed that the breakdown voltage was over 9 kV at room temperature (25 °C). The leakage currents (Ileak) at 6.5 kV are as low as 5.9×10-6 mA/cm2 (25 °C) and 9.7×10-5 mA/cm2 (150 °C). The maximum recovery loss among our switching test results was 6.7 mJ at 150 °C, 60 A. Moreover, the diodes fabricated on BPD-free area are very stable during applying 20 A current for 8~1000 h. Photoluminescence (PL) observation and KOH etching indicated that no BPD generated during improved fabrication processes.

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