scholarly journals Thermal Cycling Test and Simulation of Fan-Out Chip-Last Panel-Level Packaging for Heterogeneous Integration

2021 ◽  
Vol 18 (2) ◽  
pp. 29-39
Author(s):  
John H Lau ◽  
Cheng-Ta Ko ◽  
Chia-Yu Peng ◽  
Kai-Ming Yang ◽  
Tim Xia ◽  
...  
Keyword(s):  
Solder Joint ◽  
Thermal Cycling ◽  
Circuit Board ◽  
Heterogeneous Integration ◽  
Thermal Cycling Test ◽  
Test Results ◽  
Solder Joint Reliability ◽  
Cycling Test ◽  
Pcb Assembly ◽  
Joint Reliability

Abstract In this study, the reliability of the solder joints of a heterogeneous integration of one large chip (10 × 10 mm) and two smaller chips (7 × 5 mm) by a fan-out method with a redistribution layer-first substrate fabricated on a 515 × 510-mm panel is investigated. Emphasis is placed on the thermal cycling test (−55°C Δ 125°C, 50-min cycle) of the heterogeneous integration package on a printed circuit board (PCB). The thermal cycling test results are plotted into a Weibull distribution. The Weibull slope and characteristic life at median rank are presented. At 90% confidence, the true Weibull slope and the true 10% life interval are also provided. A linear acceleration factor is adopted to map the solder joint reliability at the test condition to the solder joint reliability at an operating condition. The failure location and failure mode of the PCB assembly of the heterogeneous integration package are provided and discussed. A nonlinear, time- and temperature-dependent 3-D finite element simulation is performed for the heterogeneous integration PCB assembly and correlated with the thermal cycling test results.

scholarly journals Thermal Cycling Test and Simulation of Six-Side Molded Panel-Level Chip-Scale Packages (PLCSPs)

2021 ◽  
Vol 18 (2) ◽  
pp. 67-80
Author(s):  
John H Lau ◽  
Cheng-Ta Ko ◽  
Chia-Yu Peng ◽  
Tzvy-Jang Tseng ◽  
Kai-Ming Yang ◽  
...  
Keyword(s):  
Solder Joint ◽  
Thermal Cycling ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Thermal Cycling Test ◽  
Test Results ◽  
Cycling Test ◽  
Chip Scale Package ◽  
C 50 ◽  
The One

Abstract In this study, the reliability of the solder joints of a six-side molded panel-level chip-scale package (PLCSP) is investigated. Emphasis is placed on the thermal cycling test (−55°C Δ 125°C, 50-min cycle) of the six-side molded PLCSP on a printed circuit board. For comparison purpose, the one without six-side molded (ordinary) PLCSP is also subjected to the same test. The thermal cycling test results are plotted into a Weibull distribution, and the true Weibull slope and true characteristic life at 90% confidence are presented. The solder joint mean life ratio of these two cases and its confidence level are also determined. Furthermore, their solder joint failure location and failure mode are provided. Finally, a nonlinear, time- and temperature-dependent 3-D finite element simulation is performed for these two cases and correlated with the thermal cycling test results.

Reliability of Fan-Out Wafer-Level Heterogeneous Integration

2018 ◽  
Vol 15 (4) ◽  
pp. 148-162 ◽  
Author(s):  
John Lau ◽  
Ming Li ◽  
Yang Lei ◽  
Margie Li ◽  
Iris Xu ◽  
...  
Keyword(s):  
Thermal Cycling ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Circuit Board ◽  
Heterogeneous Integration ◽  
Thermal Cycling Test ◽  
Wafer Level ◽  
Molding Compound ◽  
Shock Test ◽  
Cycling Test

Abstract In this study, the reliability (thermal cycling and shock) performances of a fan-out wafer-level system-in-package (SiP) or heterogeneous integration with one large chip (5 × 5 mm), three small chips (3 ×3 mm), and four capacitors (0402) embedded in an epoxy molding compound package (10 × 10 mm) with two redistribution layers (RDLs) are experimentally determined. Emphasis is placed on the estimation of the Weibull life distribution, characteristic life, and failure rate of the solder joint and RDL of this package. The fan-out wafer-level packaging is assembled on a printed circuit board (PCB) with more than 400 (Sn3wt%Ag0.5wt%Cu) solder joints. It is a six-layer PCB. The sample sizes for the thermal cycling test and shock test are, respectively, equal to 60 and 24. The failure location and modes of the thermal cycling test and shock test of the fan-out wafer-level SiP solder joints and RDLs are provided and discussed. 3-D nonlinear finite element models are also constructed and analyzed for the fan-out heterogeneous integration package during thermal cycling and shock conditions. The simulation results are correlated to the experimental results. Finally, recommendations on improving the fan-out wafer-level SiP solder joints and RDLs under thermal and shock conditions are provided.

Reliability of Fan-Out Wafer-Level Heterogeneous Integration

2018 ◽  
Vol 2018 (1) ◽  
pp. 000224-000232 ◽  
Author(s):  
John Lau ◽  
Ming Li ◽  
Yang Lei ◽  
Margie Li ◽  
Iris Xu ◽  
...  
Keyword(s):  
Thermal Cycling ◽  
Printed Circuit Board ◽  
Solder Joints ◽  
Circuit Board ◽  
Heterogeneous Integration ◽  
Thermal Cycling Test ◽  
Wafer Level ◽  
Molding Compound ◽  
Shock Test ◽  
Cycling Test

Abstract In this study, the reliability (thermal-cycling and shock) performances of a fan-out wafer-level system-in-package (SiP) or heterogeneous integration with one large chip (5mm×5mm), three small chips (3mm×3mm), and 4 capacitors (0402) embedded in an epoxy molding compound (EMC) package (10mm×10mm) with two RDLs (redistribution layers) are experimentally determined. Emphasis is placed on the estimation of the Weibull life distribution, characteristic life, and failure rate of the solder joint and RDL of this package. The fan-out wafer-level packaging (FOWLP) is assembled on a printed circuit board (PCB) with more than 400 (Sn3wt%Ag0.5wt%Cu) solder joints. It is a 6-layer PCB. The sample sizes for the thermal-cycling test and shock test are, respectively, equal to 60 and 24. The failure location and modes of the thermal-cycling test and shock test of the fan-out wafer-level SiP solder joints and RDLs are provided and discussed. 3-D nonlinear finite element models are also constructed and analyzed for the fan-out heterogeneous integration package during thermal-cycling and shock conditions. The simulation results are correlated to the experimental results. Finally, recommendations on improving the fan-out wafer-level SiP solder joints and RDLs under thermal and shock conditions are provided.

Solder Joint Reliability Modeling of WLP and FOWLP with Crack Path Evaluation Method under Thermal Cycling

2020 ◽  
Vol 2020 (1) ◽  
pp. 000001-000004
Author(s):  
Dae-Suk Kim ◽  
Karthikeyan Dhandapani
Keyword(s):  
Solder Joint ◽  
Thermal Cycling ◽  
Crack Path ◽  
Path Selection ◽  
Circuit Board ◽  
Critical Element ◽  
Wafer Level ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Wafer Level Package

Abstract An updated solder joint reliability (SJR) modeling methodology under thermal cycling (TC) is proposed and implemented for the diagonal solder crack path case as well as the SJR correlation of wafer-level package (WLP) and fan-out wafer-level package (FOWLP) data, which have the conventional solder failure mode around the under-bump metallization (UBM). First, two critical element layers near by the UBM layer and the printed circuit board (PCB) Cu pad are defined as the percentage of the total solder height in order to differentiate the critical element size around the UBM and the PCB Cu pad. Secondly, a crack path evaluation (CPE) method is developed for the gradual selection of the elements from the highest creep strain energy density (SED) value up to the predefined volume. The conventional solder crack path at the package interface or the diagonal solder crack path can be analyzed depending on the package technology because the critical solder elements are selected depending on the SED level and the failure path. The proposed SJR modeling method successfully demonstrates the diagonal solder crack path selection and further improves the SJR correlation of WLP and FOWLP.

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