Solder Joint Reliability Modeling of WLP and FOWLP with Crack Path Evaluation Method under Thermal Cycling

2020 ◽  
Vol 2020 (1) ◽  
pp. 000001-000004
Author(s):  
Dae-Suk Kim ◽  
Karthikeyan Dhandapani
Keyword(s):  
Solder Joint ◽  
Thermal Cycling ◽  
Crack Path ◽  
Path Selection ◽  
Circuit Board ◽  
Critical Element ◽  
Wafer Level ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Wafer Level Package

Abstract An updated solder joint reliability (SJR) modeling methodology under thermal cycling (TC) is proposed and implemented for the diagonal solder crack path case as well as the SJR correlation of wafer-level package (WLP) and fan-out wafer-level package (FOWLP) data, which have the conventional solder failure mode around the under-bump metallization (UBM). First, two critical element layers near by the UBM layer and the printed circuit board (PCB) Cu pad are defined as the percentage of the total solder height in order to differentiate the critical element size around the UBM and the PCB Cu pad. Secondly, a crack path evaluation (CPE) method is developed for the gradual selection of the elements from the highest creep strain energy density (SED) value up to the predefined volume. The conventional solder crack path at the package interface or the diagonal solder crack path can be analyzed depending on the package technology because the critical solder elements are selected depending on the SED level and the failure path. The proposed SJR modeling method successfully demonstrates the diagonal solder crack path selection and further improves the SJR correlation of WLP and FOWLP.

Board level solder joint reliability analysis of a fine pitch Cu post type wafer level package (WLP)

2008 ◽  
Vol 48 (4) ◽  
pp. 602-610 ◽  
Author(s):  
Xiaowu Zhang ◽  
Vaidyanathan Kripesh ◽  
T.C. Chai ◽  
Teck Chun Tan ◽  
D. Pinjala
Keyword(s):  
Solder Joint ◽  
Reliability Analysis ◽  
Wafer Level ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Fine Pitch ◽  
Board Level ◽  
Wafer Level Package

Solder joint reliability of a polymer reinforced wafer level package

2002 ◽  
Vol 42 (12) ◽  
pp. 1837-1848 ◽  
Author(s):  
Deok-Hoon Kim ◽  
Peter Elenius ◽  
Michael Johnson ◽  
Scott Barrett
Keyword(s):  
Solder Joint ◽  
Wafer Level ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Wafer Level Package

scholarly journals Thermal Cycling Test and Simulation of Fan-Out Chip-Last Panel-Level Packaging for Heterogeneous Integration

2021 ◽  
Vol 18 (2) ◽  
pp. 29-39
Author(s):  
John H Lau ◽  
Cheng-Ta Ko ◽  
Chia-Yu Peng ◽  
Kai-Ming Yang ◽  
Tim Xia ◽  
...  
Keyword(s):  
Solder Joint ◽  
Thermal Cycling ◽  
Circuit Board ◽  
Heterogeneous Integration ◽  
Thermal Cycling Test ◽  
Test Results ◽  
Solder Joint Reliability ◽  
Cycling Test ◽  
Pcb Assembly ◽  
Joint Reliability

Abstract In this study, the reliability of the solder joints of a heterogeneous integration of one large chip (10 × 10 mm) and two smaller chips (7 × 5 mm) by a fan-out method with a redistribution layer-first substrate fabricated on a 515 × 510-mm panel is investigated. Emphasis is placed on the thermal cycling test (−55°C Δ 125°C, 50-min cycle) of the heterogeneous integration package on a printed circuit board (PCB). The thermal cycling test results are plotted into a Weibull distribution. The Weibull slope and characteristic life at median rank are presented. At 90% confidence, the true Weibull slope and the true 10% life interval are also provided. A linear acceleration factor is adopted to map the solder joint reliability at the test condition to the solder joint reliability at an operating condition. The failure location and failure mode of the PCB assembly of the heterogeneous integration package are provided and discussed. A nonlinear, time- and temperature-dependent 3-D finite element simulation is performed for the heterogeneous integration PCB assembly and correlated with the thermal cycling test results.

Design and Reliability Analysis of Wafer Level Package With Bubble-Like Buffer Layer

2003 ◽  
Author(s):  
Chang-Chun Lee ◽  
Kuo-Ning Chiang
Keyword(s):  
Solder Joint ◽  
Buffer Layer ◽  
Chip Thickness ◽  
Buffer Layers ◽  
Wafer Level ◽  
Element Analysis ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Compliant Layer ◽  
Wafer Level Package

In order to enhance the wafer level package (WLP, Figure 1) reliability for larger chip size, many different kinds of WLP have been adopted, all have a compliant layer under the pads have to relieve the thermal stress of the solder joint. Usually, the solder joint reliability is enhanced with the increase of the thickness of the compliant layer. However, the fabrication processes of the WLP restrict the thickness of the compliant layer. With that in mind this research proposed a novel WLP package with bubble-like buffer layer (Figure 2) which is composed of a bubble-like plate and a buffer layer between the chip and the solder joint. The main goal of this research was to study the effects of the geometric dimensions and material properties of the bubble-like layer on the reliability of the WLP. For the parametric analysis purpose, a 2-D nonlinear finite element analysis for the proposed WLP was conducted. The results revealed that both the bubble-like plate and the buffer layer provide excellent compliant effects. However, the buffer layer has a more significant effect on enhancing the solder joint reliability. Also, for a WLP with buffer structure, the effect of the chip thickness on the reliability could be significantly reduced. In addition, the difference between the filled and non-filled buffer layers also affected the reliability of the solder joint. The results revealed that the WLP with the buffer layer and the no-fill bubble-like plate had the better reliability.

Solder Joint Reliability Simulation of Fan-out Wafer Level Package (FOWLP) Considering Viscoelastic Material Properties

2018 ◽  
Author(s):  
Zhaohui Chen ◽  
Xiaowu Zhang ◽  
Sharon Pei Siang Lim ◽  
Simon Siak Boon Lim ◽  
Boon Long Lau ◽  
...  
Keyword(s):  
Solder Joint ◽  
Viscoelastic Material ◽  
Material Properties ◽  
Wafer Level ◽  
Solder Joint Reliability ◽  
Joint Reliability ◽  
Wafer Level Package

Controlling the Solder Joint Reliability of eWLB Packages in Automotive Radar Applications Using a Design for Reliability Approach

2018 ◽  
Author(s):  
M. Niessner ◽  
G. Haubner ◽  
W. Hartner ◽  
S. Pahlke
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Wafer Level ◽  
Automotive Radar ◽  
Low Loss ◽  
Solder Joint Reliability ◽  
Design For Reliability ◽  
Joint Reliability ◽  
Ball Grid Array Packages

A DfR (Design for Reliability) approach which is systematically based on simulation, sensitivity analysis and experimental validation is applied for identifying, understanding and controlling the key factors which determine the solder joint reliability of eWLB (Embedded Wafer Level Ball Grid Array) packages that carry embedded 77 GHz dies and sit on hybrid PCB (Printed Circuit Board) stacks. The hybrid stack investigated in this work is characteristic to automotive RADAR (Radio Detection And Ranging) applications and consists of one low-loss RF (Radio Frequency) layer and several FR4 layers. In line with previous work [1], the mechanical material properties of the low-loss RF laminate material are found to be the key factor. Simulation is used to systematically screen for mechanical properties which are favorable for achieving a high solder joint reliability on the unconstrained PCBs used for standardized solder joint reliability testing. A simplified virtual assessment of PCBs constrained by the mounting in system module housings is done. Both simulation and experimental results show that RF laminate materials with low Young’s modulus are the class of materials which allows for the highest solder joint reliability for all the conditions investigated in this study.

Effects of Void, Crack, and PCB Thickness on the Solder Joint Reliability of Wafer-Level Chip-Scale Package (WLCSP) Assemblies

2002 ◽  
Author(s):  
John Lau ◽  
Yida Zou ◽  
Sergio Camerlo
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Temperature Cycling ◽  
Circuit Board ◽  
J Integral ◽  
Wafer Level ◽  
Solder Joint Reliability ◽  
Printed Circuit ◽  
Joint Reliability ◽  
Chip Scale Package

The creep analyses of solder-bumped wafer-level chip-scale package (WLCSP) on printed circuit board (PCB) subjected to temperature cycling loading are presented. Emphasis is placed on the effects of PCB thickness on the solder joint reliability of the WLCSP assembly. Also, the effects of crack-length on the crack tip characteristics such as the J-integral in the WLCSP solder joint are studied by the fracture mechanics method. Finally, the effects of voids on the crack growth in the WLCSP solder joint are investigated.

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