Thermal Cycling Test and Simulation of Six-Side Molded Panel-Level Chip-Scale Packages (PLCSPs)

Abstract In this study, the reliability of the solder joints of a six-side molded panel-level chip-scale package (PLCSP) is investigated. Emphasis is placed on the thermal cycling test (−55°C Δ 125°C, 50-min cycle) of the six-side molded PLCSP on a printed circuit board. For comparison purpose, the one without six-side molded (ordinary) PLCSP is also subjected to the same test. The thermal cycling test results are plotted into a Weibull distribution, and the true Weibull slope and true characteristic life at 90% confidence are presented. The solder joint mean life ratio of these two cases and its confidence level are also determined. Furthermore, their solder joint failure location and failure mode are provided. Finally, a nonlinear, time- and temperature-dependent 3-D finite element simulation is performed for these two cases and correlated with the thermal cycling test results.

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Thermal Cycling Test and Simulation of Fan-Out Chip-Last Panel-Level Packaging for Heterogeneous Integration

Journal of Microelectronics and Electronic Packaging ◽

10.4071/imaps.1419800 ◽

2021 ◽

Vol 18 (2) ◽

pp. 29-39

Author(s):

John H Lau ◽

Cheng-Ta Ko ◽

Chia-Yu Peng ◽

Kai-Ming Yang ◽

Tim Xia ◽

...

Keyword(s):

Solder Joint ◽

Thermal Cycling ◽

Circuit Board ◽

Heterogeneous Integration ◽

Thermal Cycling Test ◽

Test Results ◽

Solder Joint Reliability ◽

Cycling Test ◽

Pcb Assembly ◽

Joint Reliability

Abstract In this study, the reliability of the solder joints of a heterogeneous integration of one large chip (10 × 10 mm) and two smaller chips (7 × 5 mm) by a fan-out method with a redistribution layer-first substrate fabricated on a 515 × 510-mm panel is investigated. Emphasis is placed on the thermal cycling test (−55°C Δ 125°C, 50-min cycle) of the heterogeneous integration package on a printed circuit board (PCB). The thermal cycling test results are plotted into a Weibull distribution. The Weibull slope and characteristic life at median rank are presented. At 90% confidence, the true Weibull slope and the true 10% life interval are also provided. A linear acceleration factor is adopted to map the solder joint reliability at the test condition to the solder joint reliability at an operating condition. The failure location and failure mode of the PCB assembly of the heterogeneous integration package are provided and discussed. A nonlinear, time- and temperature-dependent 3-D finite element simulation is performed for the heterogeneous integration PCB assembly and correlated with the thermal cycling test results.

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Reliability of Fan-Out Wafer-Level Heterogeneous Integration

Journal of Microelectronics and Electronic Packaging ◽

10.4071/imaps.728940 ◽

2018 ◽

Vol 15 (4) ◽

pp. 148-162 ◽

Cited By ~ 9

Author(s):

John Lau ◽

Ming Li ◽

Yang Lei ◽

Margie Li ◽

Iris Xu ◽

...

Keyword(s):

Thermal Cycling ◽

Printed Circuit Board ◽

Solder Joints ◽

Circuit Board ◽

Heterogeneous Integration ◽

Thermal Cycling Test ◽

Wafer Level ◽

Molding Compound ◽

Shock Test ◽

Cycling Test

Abstract In this study, the reliability (thermal cycling and shock) performances of a fan-out wafer-level system-in-package (SiP) or heterogeneous integration with one large chip (5 × 5 mm), three small chips (3 ×3 mm), and four capacitors (0402) embedded in an epoxy molding compound package (10 × 10 mm) with two redistribution layers (RDLs) are experimentally determined. Emphasis is placed on the estimation of the Weibull life distribution, characteristic life, and failure rate of the solder joint and RDL of this package. The fan-out wafer-level packaging is assembled on a printed circuit board (PCB) with more than 400 (Sn3wt%Ag0.5wt%Cu) solder joints. It is a six-layer PCB. The sample sizes for the thermal cycling test and shock test are, respectively, equal to 60 and 24. The failure location and modes of the thermal cycling test and shock test of the fan-out wafer-level SiP solder joints and RDLs are provided and discussed. 3-D nonlinear finite element models are also constructed and analyzed for the fan-out heterogeneous integration package during thermal cycling and shock conditions. The simulation results are correlated to the experimental results. Finally, recommendations on improving the fan-out wafer-level SiP solder joints and RDLs under thermal and shock conditions are provided.

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Reliability of Fan-Out Wafer-Level Heterogeneous Integration

International Symposium on Microelectronics ◽

10.4071/2380-4505-2018.1.000224 ◽

2018 ◽

Vol 2018 (1) ◽

pp. 000224-000232 ◽

Cited By ~ 1

Author(s):

John Lau ◽

Ming Li ◽

Yang Lei ◽

Margie Li ◽

Iris Xu ◽

...

Keyword(s):

Thermal Cycling ◽

Printed Circuit Board ◽

Solder Joints ◽

Circuit Board ◽

Heterogeneous Integration ◽

Thermal Cycling Test ◽

Wafer Level ◽

Molding Compound ◽

Shock Test ◽

Cycling Test

Abstract In this study, the reliability (thermal-cycling and shock) performances of a fan-out wafer-level system-in-package (SiP) or heterogeneous integration with one large chip (5mm×5mm), three small chips (3mm×3mm), and 4 capacitors (0402) embedded in an epoxy molding compound (EMC) package (10mm×10mm) with two RDLs (redistribution layers) are experimentally determined. Emphasis is placed on the estimation of the Weibull life distribution, characteristic life, and failure rate of the solder joint and RDL of this package. The fan-out wafer-level packaging (FOWLP) is assembled on a printed circuit board (PCB) with more than 400 (Sn3wt%Ag0.5wt%Cu) solder joints. It is a 6-layer PCB. The sample sizes for the thermal-cycling test and shock test are, respectively, equal to 60 and 24. The failure location and modes of the thermal-cycling test and shock test of the fan-out wafer-level SiP solder joints and RDLs are provided and discussed. 3-D nonlinear finite element models are also constructed and analyzed for the fan-out heterogeneous integration package during thermal-cycling and shock conditions. The simulation results are correlated to the experimental results. Finally, recommendations on improving the fan-out wafer-level SiP solder joints and RDLs under thermal and shock conditions are provided.

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Improving WLCSP Reliability Through Solder Joint Geometry Optimization

International Symposium on Microelectronics ◽

10.4071/isom-2013-wa45 ◽

2013 ◽

Vol 2013 (1) ◽

pp. 000546-000550 ◽

Cited By ~ 5

Author(s):

Boyd Rogers ◽

Chris Scanlan

Keyword(s):

Solder Joint ◽

Thermal Cycling ◽

Printed Circuit Board ◽

Geometry Optimization ◽

Circuit Board ◽

Wafer Level ◽

Joint Geometry ◽

Chip Scale Package ◽

Large Platform ◽

Board Level

The effects of solder joint geometry on wafer-level chip-scale package reliability have been studied both through simulations and board level reliability testing. In reliability tests on a 3.9×3.9mm2 die, an enhancement of nearly 2× in thermal cycling reliability was achieved by optimizing the solder joint and under-bump pad stack. In particular, undersizing the printed circuit board pad to produce a more spherical solder joint and reducing the polymer via size under the bump appear to be very important for improving thermal cycling results. Data collected here shows that joint geometry changes can be implemented without compromising drop performance. Methods learned were applied to the qualification of a 6.0×6.0mm2 die, a large platform for WLCSP applications.

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Nonlinear-Time-Dependent Analysis of Micro Via-In-Pad Substrates for Solder Bumped Flip Chip Applications

Journal of Electronic Packaging ◽

10.1115/1.1462626 ◽

2002 ◽

Vol 124 (3) ◽

pp. 205-211 ◽

Cited By ~ 12

Author(s):

John H. Lau ◽

S. W. Ricky Lee ◽

Stephen H. Pan ◽

Chris Chang

Keyword(s):

Cross Sections ◽

Flip Chip ◽

Printed Circuit Board ◽

Low Cost ◽

Circuit Board ◽

Test Results ◽

Pcb Assembly ◽

Creep Analysis ◽

Chip Scale Package ◽

Time Dependent Analysis

An elasto-plastic-creep analysis of a low-cost micro via-in-pad (VIP) substrate for supporting a solder bumped flip chip in a chip scale package (CSP) format which is soldered onto a printed circuit board (PCB) is presented in this study. Emphasis is placed on the design, materials, and reliability of the micro VIP substrate and of the micro VIP CSP solder joints on PCB. The solder is assumed to obey Norton’s creep law. Cross-sections of samples are examined for a better understanding of the solder bump, CSP substrate redistribution, micro VIP, and solder joint. Also, the thermal cycling test results of the micro VIP CSP PCB assembly is presented.

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Causes of Degradation of Thermal Performance of Ball Grid Arrays After Thermal Cycling

ASME 2007 InterPACK Conference, Volume 2 ◽

10.1115/ipack2007-33626 ◽

2007 ◽

Author(s):

Roy W. Knight ◽

Yasser Elkady ◽

Jeffrey C. Suhling ◽

Pradeep Lall

Keyword(s):

Solder Joint ◽

Thermal Resistance ◽

Thermal Cycling ◽

Thermal Performance ◽

Printed Circuit Board ◽

Circuit Board ◽

Element Analysis ◽

Solder Balls ◽

Ball Grid Array Packages ◽

The Impact

The thermal performance of Ball Grid Array packages depends upon many parameters including die size, use of thermal balls, number of perimeter balls, use of underfill, and printed circuit board heat spreader and thermal via design. Thermal cycling can affect the integrity of thermal paths in and around the BGA as a result of the cracking of solder balls and delamination of the package, including at underfill interfaces. In this study, the impact of thermal cycling on the thermal performance of BGA’s was investigated and quantified. A number of test boards which included a range of the parameters cited above were experimentally examined. A baseline thermal resistance was measured for each case, which was verified with numerical thermal modeling. The boards were then subjected to thermal cycling from −40°C to 125°C. Every 250 cycles the thermal performance was measured. Packages expected to be least reliable (with large die and no underfill), showed an increase in thermal resistance after 750 thermal cycles. Further increases in thermal resistance were observed with continuous thermal cycling until solder joint failure occurred at 1250 cycles, preventing additional measurements. Finite element analysis identified critical thermal and perimeter solder balls as the most likely sites for cracking. Boards were cross-sectioned and examined for solder joint cracks and delamination to identify the cause for the observed increases in thermal resistance. Cracking was found in the critical thermal and perimeter solder balls.

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