Extended High-Temperature Operation of Silicon Carbide CMOS Circuits for Venus Surface Application

2016 ◽  
Vol 13 (4) ◽  
pp. 143-154 ◽  
Author(s):  
Jim Holmes ◽  
A. Matthew Francis ◽  
Ian Getreu ◽  
Matthew Barlow ◽  
Affan Abbasi ◽  
...  

In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circuits for extended periods (up to 100 h) are presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at extreme temperatures for any period. Based on these results, Venus nominal temperature (470°C) transistor models and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller. A 16-bit microcontroller, based on the OpenMSP 16-bit core, is demonstrated through physical design and simulation in SiC-CMOS, with an eye for Venus as well as terrestrial applications.

2016 ◽  
Vol 2016 (HiTEC) ◽  
pp. 000242-000248 ◽  
Author(s):  
A. Matthew Francis ◽  
Jim Holmes ◽  
Nick Chiolino ◽  
Matthew Barlow ◽  
Affan Abbasi ◽  
...  

Abstract In the last decade, significant effort has been expended towards the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field effect transistors and metal-oxide-semiconductor field effect transistors have been pursued and demonstrated. More recently1,2, advances in low-power complementary MOS devices have enabled the development of highly-integrated digital, analog and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) for extended periods (up to 100 hours) of several building block circuits will be presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at these extreme temperatures for any period of time. Based on these results, Venus nominal temperature (470°C) SPICE m°dels and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller in SiC-CMOS, with an eye for Venus as well as terrestrial applications.


2012 ◽  
Vol 2012 (HITEC) ◽  
pp. 000373-000377 ◽  
Author(s):  
E.P Ramsay ◽  
D.T. Clark ◽  
J.D. Cormack ◽  
A.E. Murphy ◽  
D.A Smith ◽  
...  

A need for high temperature integrated circuits is emerging in a number of application areas. As Silicon Carbide power discrete devices become more widely available, there is a growing need for control ICs capable of operating at the same temperatures and mounted on the same modules. Also, the use of high temperature sensors, in, for example, aero engines and in deep hydrocarbon and geothermal drilling applications results in a demand for high temperature sensor interface ICs. This paper presents new results on a range of simple logic and analogue circuits fabricated on a developing Silicon Carbide CMOS process which is intended for mixed signal integrated circuit applications such as those above. A small family of logic circuits, pin compatible with the 74xx series TTL logic parts, has been designed, fabricated and tested and includes, for example, a Quad Nand gate and a Dual D-type flip-flop. These have been found to be functional from room temperature up to 400°C. Analogue blocks have been investigated with a view to using switched capacitor or autozero techniques to compensate for temperature and time induced drifts, allowing very high temperature operation.


2005 ◽  
Vol 97 (4) ◽  
pp. 046106 ◽  
Author(s):  
Stephen K. Powell ◽  
Neil Goldsman ◽  
Aivars Lelis ◽  
James M. McGarrity ◽  
Flynn B. McLean

Sensors ◽  
2020 ◽  
Vol 20 (17) ◽  
pp. 4731
Author(s):  
Wei-Ren Chen ◽  
Yao-Chuan Tsai ◽  
Po-Jen Shih ◽  
Cheng-Chih Hsu ◽  
Ching-Liang Dai

The fabrication and characterization of a magnetic micro sensor (MMS) with two magnetic field effect transistors (MAGFETs) based on the commercial complementary metal oxide semiconductor (CMOS) process are investigated. The magnetic micro sensor is a three-axis sensing type. The structure of the magnetic microsensor is composed of an x/y-MAGFET and a z-MAGFET. The x/y-MAGFET is employed to sense the magnetic field (MF) in the x- and y-axis, and the z-MAGFET is used to detect the MF in the z-axis. To increase the sensitivity of the magnetic microsensor, gates are introduced into the two MAGFETs. The sensing current of the MAGFET enhances when a bias voltage is applied to the gates. The finite element method software Sentaurus TCAD was used to analyze the MMS’s performance. Experiments show that the MMS has a sensitivity of 182 mV/T in the x-axis MF and a sensitivity of 180 mV/T in the y-axis MF. The sensitivity of the MMS is 27.8 mV/T in the z-axis MF.


2011 ◽  
Vol 50 (1S1) ◽  
pp. 01AD03 ◽  
Author(s):  
Takayuki Sugiyama ◽  
Hiroshi Amano ◽  
Daisuke Iida ◽  
Motoaki Iwaya ◽  
Satoshi Kamiyama ◽  
...  

2011 ◽  
Vol 679-680 ◽  
pp. 445-448 ◽  
Author(s):  
Muneharu Kato ◽  
Yuichiro Nanen ◽  
Jun Suda ◽  
Tsunenobu Kimoto

Post-oxidation annealing (POA) in Ar at high temperature has been performed during fabrication of 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). The gate oxides were formed by thermal oxidation followed by N2O annealing, then annealed in Ar for 30 min or 5 h at 1300 °C. The results of Secondary Ion Mass Spectrometry (SIMS) measurements indicated that the C atoms accumulated at the SiO2/SiC interface by thermal oxidation diffused during the 5h-Ar annealing. The characteristics of n-channel MOSFETs were improved and the peak value of field effect mobility was increased to 33 cm2/Vs from 19 cm2/Vs by extending the Ar annealing time.


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