Improved Characteristics of SiC MOSFETs by Post-Oxidation Annealing in Ar at High Temperature

2011 ◽  
Vol 679-680 ◽  
pp. 445-448 ◽  
Author(s):  
Muneharu Kato ◽  
Yuichiro Nanen ◽  
Jun Suda ◽  
Tsunenobu Kimoto

Post-oxidation annealing (POA) in Ar at high temperature has been performed during fabrication of 4H-SiC metal-oxide-semiconductor field-effect transistors (MOSFETs). The gate oxides were formed by thermal oxidation followed by N2O annealing, then annealed in Ar for 30 min or 5 h at 1300 °C. The results of Secondary Ion Mass Spectrometry (SIMS) measurements indicated that the C atoms accumulated at the SiO2/SiC interface by thermal oxidation diffused during the 5h-Ar annealing. The characteristics of n-channel MOSFETs were improved and the peak value of field effect mobility was increased to 33 cm2/Vs from 19 cm2/Vs by extending the Ar annealing time.

2005 ◽  
Vol 97 (4) ◽  
pp. 046106 ◽  
Author(s):  
Stephen K. Powell ◽  
Neil Goldsman ◽  
Aivars Lelis ◽  
James M. McGarrity ◽  
Flynn B. McLean

2016 ◽  
Vol 13 (4) ◽  
pp. 143-154 ◽  
Author(s):  
Jim Holmes ◽  
A. Matthew Francis ◽  
Ian Getreu ◽  
Matthew Barlow ◽  
Affan Abbasi ◽  
...  

In the last decade, significant effort has been expended toward the development of reliable, high-temperature integrated circuits. Designs based on a variety of active semiconductor devices including junction field-effect transistors and metal-oxide-semiconductor (MOS) field-effect transistors have been pursued and demonstrated. More recently, advances in low-power complementary MOS (CMOS) devices have enabled the development of highly integrated digital, analog, and mixed-signal integrated circuits. The results of elevated temperature testing (as high as 500°C) of several building block circuits for extended periods (up to 100 h) are presented. These designs, created using the Raytheon UK's HiTSiC® CMOS process, present the densest, lowest-power integrated circuit technology capable of operating at extreme temperatures for any period. Based on these results, Venus nominal temperature (470°C) transistor models and gate-level timing models were created using parasitic extracted simulations. The complete CMOS digital gate library is suitable for logic synthesis and lays the foundation for complex integrated circuits, such as a microcontroller. A 16-bit microcontroller, based on the OpenMSP 16-bit core, is demonstrated through physical design and simulation in SiC-CMOS, with an eye for Venus as well as terrestrial applications.


MRS Bulletin ◽  
2005 ◽  
Vol 30 (4) ◽  
pp. 293-298 ◽  
Author(s):  
Jian H. Zhao

AbstractSilicon carbide power field-effect transistors, including power vertical-junction FETs (VJFETs) and metal oxide semiconductor FETs (MOSFETs), are unipolar power switches that have been investigated for high-temperature and high-power-density applications. Recent progress and results will be reviewed for different device designs such as normally-OFF and normally-ON VJFETs, double-implanted MOSFETs, and U-shaped-channel MOSFETs. The advantages and disadvantages of SiC VJFETs and MOSFETs will be discussed. Remaining challenges will be identified.


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