Handling technology for 0.075-square mm powder IC chip

2012 ◽  
Vol 2012 (1) ◽  
pp. 000975-000983
Author(s):  
Hideyuki Noda

We have developed a packaging technology for powder IC chip of 0.075-square mm × 5 μm thickness. The chip, which can be embedded into papers, is expected to be a key device in pioneering new markets, where it can cheaply and easily manage a number of articles and identify papers such as securities. Manipulating a fine chip in a dry environment has been difficult due to adhesion of the other chips and scattering from the influence of electrostatic phenomena. However, using the micro-bead and cell trapping technology, it is possible to put the chips on a substrate one by one. The technique uses a double-surface-electrode chip, and a novel water-based chip handling technique composed of a micropipette manipulation and a self-aligned positioning. The double-surface-electrode structure that has two individual surface electrodes is advantageous in that when mounting the powder chip on a substrate, the chips are placed on the substrate without the need for highly accurate positioning, including the chip orientation control (upside-down, rotation). As for the micropipette manipulation, the chips are kept dispersed by stirring liquid with addition of a 0.5% surfactant to prevent chips from sticking together, and a flat-end glass micropipette successfully manipulated a single chip with high chip-capturing ratio. The self-aligned positioning of the chip uses micro liquid droplet shrinkage during evaporation process. The chip was able to move together with the droplet edge, and was positioned in the predefined hydrophilic domain. The liquid cushioning pick-up and placing action enables stress-free handling.

2014 ◽  
Vol 884-885 ◽  
pp. 283-286
Author(s):  
Hai Kuang ◽  
Shi An He ◽  
Ying Luo ◽  
Xiang Qing Zhang ◽  
Zhi Hua Xiong

Before cutting into a single chip, we have tested LED chip with different electrode that is produced under the same condition. With drive current changes, comparing the intensity of light emission of LED chip and operating voltage about the two samples. The conclusion shows that the shape of electrode makes influence on the performance of LED, and the performance of circular electrode with angle is better. The result demonstrates that the better electrode structure of LED chip can improve its performance.


2018 ◽  
Vol 1 (1) ◽  
pp. 23
Author(s):  
Xudong Ding ◽  
Hongyan Jiang ◽  
Weihua Zhou

<p>With the development of electronic technology, medical equipment is also undergoing some changes, and the traditional manual monitoring mode is clearly unsatisfied with today’s monitoring needs. At present, China’s medical institutions in the infusion treatment, the infusion rate control or the use of conventional clinical infusion, general use of hanging bottle infusion, and direct observation with the eyes, relying on manual clip to control the infusion rate, this mode of operation cannot be precisely controlled Infusion speed, and the workload. Therefore, the need for both cheap and practical medical infusion detection monitoring device to meet today’s medical needs. The system is designed with the single chip AT89C51 as the core, the keyboard and photoelectric sensor as the input system to digital tube and motor as the output system of intelligent infusion control and monitoring system. The keyboard system is a stand-alone key system, the function of the photoelectric sensor for the liquid droplet speed and infusion bottle page height of the reliable detection. When the liquid level is below the alert value, the system issues an alarm and can manually remove the alarm. The motor has a large controllable power and the input pulse can be maintained when the same torque and other advantages, so that you can control the bottle by the upper and lower slowly to achieve the purpose of intelligent control of liquid drip speed.</p>


2019 ◽  
Vol 13 (3) ◽  
pp. 5334-5346
Author(s):  
M. N. Nguyen ◽  
L. Q. Nguyen ◽  
H. M. Chu ◽  
H. N. Vu

In this paper, we report on a SOI-based comb capacitive-type accelerometer that senses acceleration in two lateral directions. The structure of the accelerometer was designed using a proof mass connected by four folded-beam springs, which are compliant to inertial displacement causing by attached acceleration in the two lateral directions. At the same time, the folded-beam springs enabled to suppress cross-talk causing by mechanical coupling from parasitic vibration modes. The differential capacitor sense structure was employed to eliminate common mode effects. The design of gap between comb fingers was also analyzed to find an optimally sensing comb electrode structure. The design of the accelerometer was carried out using the finite element analysis. The fabrication of the device was based on SOI-micromachining. The characteristics of the accelerometer have been investigated by a fully differential capacitive bridge interface using a sub-fF switched-capacitor integrator circuit. The sensitivities of the accelerometer in the two lateral directions were determined to be 6 and 5.5 fF/g, respectively. The cross-axis sensitivities of the accelerometer were less than 5%, which shows that the accelerometer can be used for measuring precisely acceleration in the two lateral directions. The accelerometer operates linearly in the range of investigated acceleration from 0 to 4g. The proposed accelerometer is expected for low-g applications.


MRS Bulletin ◽  
1997 ◽  
Vol 22 (10) ◽  
pp. 19-27 ◽  
Author(s):  
Wei William Lee ◽  
Paul S. Ho

Continuing improvement of microprocessor performance historically involves a decrease in the device size. This allows greater device speed, an increase in device packing density, and an increase in the number of functions that can reside on a single chip. However higher packing density requires a much larger increase in the number of interconnects. This has led to an increase in the number of wiring levels and a reduction in the wiring pitch (sum of the metal line width and the spacing between the metal lines) to increase the wiring density. The problem with this approach is that—as device dimensions shrink to less than 0.25 μm (transistor gate length)—propagation delay, crosstalk noise, and power dissipation due to resistance-capacitance (RC) coupling become significant due to increased wiring capacitance, especially interline capacitance between the metal lines on the same metal level. The smaller line dimensions increase the resistivity (R) of the metal lines, and the narrower interline spacing increases the capacitance (C) between the lines. Thus although the speed of the device will increase as the feature size decreases, the interconnect delay becomes the major fraction of the total delay and limits improvement in device performance.To address these problems, new materials for use as metal lines and interlayer dielectrics (ILD) as well as alternative architectures have been proposed to replace the current Al(Cu) and SiO2 interconnect technology.


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