scholarly journals Characterization of a Novel Low-Power SRAM Bit-Cell Structure at Deep Sub-Micron CMOS Technology for Multimedia Applications

2012 ◽  
Vol 03 (01) ◽  
pp. 23-28 ◽  
Author(s):  
Rakesh Kumar Singh ◽  
Manisha Pattanaik ◽  
Neeraj Kr. Shukla
Keyword(s):  
Low Power ◽  
Cell Structure ◽  
Cmos Technology ◽  
Multimedia Applications

Analysis of an Anomalous Transistor Exhibiting Dual-Vt Characteristics and Its Cause in a 90nm Node CMOS Technology

2012 ◽  
Author(s):  
Yuk L. Tsang ◽  
Xiang D. Wang ◽  
Reyhan Ricklefs ◽  
Jason Goertz
Keyword(s):  
Threshold Voltage ◽  
Electrical Characterization ◽  
Cmos Technology ◽  
Short Channel ◽  
Visual Defect ◽  
Subthreshold Region ◽  
Short Channel Effect ◽  
Channel Effect ◽  
Transistor Model

Abstract In this paper, we report a transistor model that has successfully led to the identification of a non visual defect. This model was based on detailed electrical characterization of a MOS NFET exhibiting a threshold voltage (Vt) of just about 40mv lower than normal. This small Vt delta was based on standard graphical extrapolation method in the usual linear Id-Vg plots. We observed, using a semilog plot, two slopes in the Id-Vg curves with Vt delta magnified significantly in the subthreshold region. The two slopes were attributed to two transistors in parallel with different Vts. We further found that one of the parallel transistors had short channel effect due to a punch-through mechanism. It was proposed and ultimately confirmed the cause was due to a dopant defect using scanning capacitance microscopy (SCM) technique.

Preparation and Characterization of Soybean Oil-based Flame Retardant Rigid Polyurethane Foams Containing Phosphaphenanthrene Groups

2020 ◽  
Vol 17 (10) ◽  
pp. 760-771
Author(s):  
Qirui Gong ◽  
Niangui Wang ◽  
Kaibo Zhang ◽  
Shizhao Huang ◽  
Yuhan Wang
Keyword(s):  
Soybean Oil ◽  
Flame Retardant ◽  
Chemical Structure ◽  
Cell Structure ◽  
Polyurethane Foams ◽  
Limiting Oxygen Index ◽  
Rigid Polyurethane Foams ◽  
Degradation Activation Energy ◽  
Ft Ir

A phosphaphenanthrene groups containing soybean oil based polyol (DSBP) was synthesized by epoxidized soybean oil (ESO) and 9,10-dihydro-oxa-10-phosphaphenanthrene-10-oxide (DOPO). Soybean oil based polyol (HSBP) was synthesized by ESO and H2O. The chemical structure of DSBP and HSBP were characterized with FT-IR and 1H NMR. The corresponding rigid polyurethane foams (RPUFs) were prepared by mixing DSBP with HSBP. The results revealed apparent density and compression strength of RPUFs decreased with increasing the DSBP content. The cell structure of RPUFs was examined by scanning electron microscope (SEM) which displayed the cells as spherical or polyhedral. The thermal degradation and flame retardancy of RPUFs were investigated by thermogravimetric analysis, limiting oxygen index (LOI), and UL 94 vertical burning test. The degradation activation energy (Ea) of first degradation stage reduced from 80.05 kJ/mol to 37.84 kJ/mol with 80 wt% DSBP. The RUPF with 80 wt% DSBP achieved UL94 V-0 rating and LOI 28.3. The results showed that the flame retardant effect was mainly in both gas phase and condensed phase.

scholarly journals The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

2021 ◽  
Vol 11 (1) ◽  
pp. 429
Author(s):  
Min-Su Kim ◽  
Youngoo Yang ◽  
Hyungmo Koo ◽  
Hansik Oh
Keyword(s):  
Integrated Circuits ◽  
Embedded System ◽  
Low Power ◽  
High Speed ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Clock Generation ◽  
Allocation Method ◽  
Evaluation Board ◽  
28 Nm

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

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