scholarly journals A Decoder – Look up Tables for FPGAs

2021 ◽  
pp. 365-373
Author(s):  
Sergey F. Tyurin ◽  
Ruslan V. Vikhorev
Keyword(s):  
Adaptive Logic ◽  
Logic Device ◽  
Logic Function ◽  
Large N ◽  
Current Consumption ◽  
Field Programmable ◽  
Pass Transistor ◽  
Logic Modules ◽  
Further Development ◽  
Logic Array

The FPGA (Field-Programmable Gate Array) has recently become the popular hardware and so-called LUTs (Look up Tables) are the basic of the FPGAs logic. For example, n-LUT is the MOS pass transistors multiplexer 2n-1 which input data receive SRAM cells logic function configuration (user’s projects Truth Table). Address inputs of the LUT are the variables. Therefore, we get one n-arguments logic function for the actual FPGA configuration. To get m functions (even with the same n-arguments) we should take m LUT. Authors propose a novel Decoder n-LUT (n-DC LUT), which makes possible to get m functions with the same n-arguments, like in Program Logic Array (PLA) CPLD (Complex Programmable Logic Device). DC LUT activates one of the 2n product terms outputs. Combined with OR product terms we can get m functions with the same n-arguments. To do this option we can use, for example, FPGAs typical connections units. The restriction of Meade-Conway for the FPGAs allows n=3 in one tree. Two 3-LUTs with one 1-LUTs form 4-LUT. Modern Adaptive Logic Modules (ALM) have n=8, but not all possible functions are implemented. The article deals with the design and investigation of some variants 3-DC LUT: with pull up output resistors, with orthogonal output circuits, with orthogonal transistors for each pass transistor. Simulation confirms the feasibility of the proposed method and shows that DC LUT with orthogonal output circuits is better variant of the systems realization in terms of current consumption and time delay at large n. A further development of the ALM concept may be the introduction of adaptive DC LUT, which, by tuning, can calculate single LUT function or 2n decoder functions. The proposed elements allow to increase the functionality of the FPGAs.

Programmable Logic Gates Based on Tunable Multistable Mechanisms

2019 ◽  
Author(s):  
Mohamed Zanaty ◽  
Hubert Schneegans ◽  
Ilan Vardi ◽  
Simon Henein
Keyword(s):  
Logic Gate ◽  
Logic Gates ◽  
Building Blocks ◽  
Programmable Logic ◽  
Logic Device ◽  
Logic Function ◽  
Element Analysis ◽  
Stability Behavior ◽  
Binary Logic ◽  
Logical Operations

Abstract Binary logic operations are the building blocks of computing machines. In this paper, we present a new programmable binary logic gate based on programmable multistable mechanisms (PMM), which are multistable structures whose stability behavior depends on modifiable boundary conditions as defined and analyzed in our previous work. The logical state of a PMM is defined by its stability and logical operations are implemented by modifying the stability behavior of the mechanism. Our programmable logic device has two qualitatively different sets of inputs. The first set determines the logic function to be computed. The second set represents the logical inputs. The output is a single logical value, “true” if the mechanism changes state and “false” otherwise. In this way, we are able to mechanically implement a set of binary logical operations. This implementation is validated using an analytical model characterizing the qualitative stability behavior of the mechanism. This was further verified using finite element analysis and experimental demonstration.

Research on Dual Buck Half Bridge Five-Level Inverter for Rooftop Solar System

2011 ◽  
Vol 99-100 ◽  
pp. 628-632
Author(s):  
Bao Jian Ji ◽  
Feng Hong ◽  
Wen Jing Ge ◽  
Wei Yang
Keyword(s):  
Pulse Width Modulation ◽  
Sine Wave ◽  
Logic Device ◽  
Wave Generator ◽  
Field Programmable ◽  
Simulation And Experiment ◽  
And Performance ◽  
Sine Wave Generator ◽  
Sinusoidal Pulse Width Modulation ◽  
Novel Design

This paper presents a novel design for dual buck half bridge five-level inverter (DBHBFLI), which based on field-programmable gate array (FPGA), and was used for photovoltaic power system. This topology is derived from dual buck half bridge inverter (DBHBI), which has the characteristics of no shoot-through problem, no body diode reverse-recovery problem, and current half-period work mode, these merits are retained in the proposed inverter. FPGA logic device is chosen for the hardware implementation of control circuit. The FPGA controller consists of six main modules: the sine wave generator module, the triangle wave generator module, the voltage proportion integration (PI) module, the current proportion (P) module, sinusoidal pulse width modulation (SPWM) module, and SPWM distribution module. VHDL is used in the design of each module. The simulation and experiment results which confirm the validity and performance of the design are shown in the paper.

Embedding the Digital Watermarks into FPGA-Projects Containing the Adaptive Logic Modules

2019 ◽  
Author(s):  
Kostiantyn Zashcholkin ◽  
Oleksandr Drozd ◽  
Olena Ivanova ◽  
Ruslan Shaporin ◽  
Olga Veselska ◽  
...  
Keyword(s):  
Adaptive Logic ◽  
Digital Watermarks ◽  
Logic Modules

Simulation and Application of PLD in Electric Power System Circuit

2012 ◽  
Vol 241-244 ◽  
pp. 1931-1935
Author(s):  
Cheng Liu ◽  
Zhe Li ◽  
Jia Jia Hou
Keyword(s):  
Power System ◽  
Electric Power ◽  
Electric Power System ◽  
Circuit Board ◽  
Programmable Logic ◽  
Logic Device ◽  
Small Current ◽  
Programmable Logic Device ◽  
Field Programmable ◽  
Hardware Circuit

Programmable Logic Device(PLD) has been widely used in hardware circuit, and it has evolved into two types: Complex Programmable Logic Device(CPLD) and Field Programmable Gate Array(FPGA). This paper takes small current grounding in electric power system as background, uses xc95144, a representative CPLD of Xilinx Company in the signal collecting circuit to collect voltage and current signals, and do some other operations to spare circuit board area. This paper also tries to translate the schematic into VHDL-described text and do simulation to the text.

scholarly journals PROJETO E IMPLEMENTAÇÃO DE FILTRO DE KALMAN EMBARCADO EM FPGA PARA O RASTREIO DE FOGUETES BALÍSTICOS

2014 ◽  
pp. 149
Author(s):  
Madson Cruz Machado ◽  
João Viana da Fonseca Neto ◽  
José Alano Peres Abreu
Keyword(s):  
Kalman Filter ◽  
Real Data ◽  
Field Programmable Gate Arrays ◽  
High Accuracy ◽  
Programmable Logic ◽  
Logic Device ◽  
Filtering Algorithm ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays

Neste trabalho faz-se uma abordagem acerca do fiiltro de Kalman no que tange a sua concep-ção, modelamento matemático, algoritmo de fiiltragem e implementação em FPGA (Field Programmable Gate Arrays). Faz-se também um breve estudo sobre o dispositivo lógico programável (PLD) do tipo FPGA, sua arquitetura e suas aplicações. Após o estudo acerca do fiiltro de Kalman e sobre FPGA pas-sa-se para a etapa de embarcar o fiiltro em hardware do tipo FPGA explorando as suas características de processamento paralelo. A etapa fiinal é a validação do fiiltro executando o algoritmo de fiiltragem em FPGA usando dados reais de lançamento de foguetes balísticos. Os dados foram fornecidos pelo Centro de Lançamento de Alcântara (CLA). A principal contribuição deste trabalho é a implementação de uma arquitetura FPGA reconfigurável, garantindo uma plataforma rápida o suficiente para radares com alta precisão e boa capacidade de rastreamento de foguetes.Palavras-chave: Filtro de Kalman. FPGA. Lançamento de foguete. Filtragem.DESIGN AND IMPLEMENTATION OF KALMAN FILTER EMBEDDED IN FPGA FOR TRACKING OF BALLISTIC ROCKETABSTRACT: This work is an approach about the Kalman filter with respect to its design, mathematical modeling, filtering algorithm and implementation in FPGA (Field Programmable Gate Arrays). Also make a brief study on the programmable logic device (PLD) type FPGA, its architecture and its applications. After the study of the Kalman filter on FPGA and passes to the step of embedded on the filter in FPGA type hardware exploring its features parallel processing. The final step is to validate the filter running filtering algorithm in FPGA using real data from launching ballistic rockets. The data were provided by the Alcan-tara Launch Center (CLA). The main contribution of this work is the implementation of a reconfigurable FPGA architecture, ensuring fast enough to radar platform with high accuracy and good tracking capability rockets.KEYWORDS: Kalman filter. FPGA. Rocket launching. Filtering.DISEÑO E IMPLEMENTACIÓN DE FILTRO KALMAN EMBARCARON EN FPGA PARA DETECCIÓN DE ROCKET BALLISTICRESUMEN: Este trabajo es un enfoque sobre el filtro de Kalman con respecto a su diseño, el modelado matemático y la implementación algoritmo de filtrado en FPGA (Field Programmable Gate Arrays). Tambi-én hace un breve estudio sobre el dispositivo lógico programable (PLD) tipo FPGA, su arquitectura y sus aplicaciones. Tras el estudio del filtro de Kalman en FPGA pasa a la etapa de embarcarse en la FPGA hardware tipo de filtro explorar sus características de procesamiento paralelo. El último paso es validar el filtro funcionando algoritmo de filtrado en FPGA utilizando datos reales de lanzamiento de cohetes balísti-cos. Los datos fueron proporcionados por el Centro de Lanzamiento de Alcántara (CLA). La principal con-tribución de este trabajo es la implementación de una arquitectura FPGA reconfigurable, asegurando la suficiente rapidez a la plataforma de radar con alta precisión y buenos cohetes capacidad de seguimiento.PALABRAS CLAVE: Filtro de Kalman. FPGA. Cohete de lanzamiento. El filtrado.

scholarly journals Design and Construction of 3 x 3 Bits Programmable Logic Array (PLA) Circuit

2020 ◽  
pp. 179-183
Author(s):  
Sanda Win ◽  
San San Htwe ◽  
Sandar Win ◽  
Myint Myint Swe
Keyword(s):  
Logic Circuits ◽  
Programmable Logic ◽  
Canonical Forms ◽  
Logic Device ◽  
Programmable Logic Array ◽  
Sum Of Products ◽  
Combinational Logic Circuits ◽  
Input Variables ◽  
Logic Functions ◽  
Logic Array

A programmable logic array (PLA) is a kind of programmable logic device used to implement combinational logic circuits. The PLA has a set of programmable AND gate planes, which link to a set of programmable OR gate planes, which can then be conditionally complemented to produce an output. It has 2N AND gate s for N input variables and for M outputs from PLA, there should be M OR gates, each with programmable inputs from all of the AND gates. This layout allows for many logic functions to be synthesized in the sum of products canonical forms. The Programmable Logic Array (PLA) has a programmable AND array followed by a programmable OR array. Programmable Logic Array (PLA) circuit is built by using AND gates and OR gates. The 3x 4 bits data can be stored in this circuit. The large storage data bits of PLA circuit store by a using large AND-OR array with lots of inputs and product terms, and programmable connections. Programmable Logic Array circuit functions as ROM circuit.

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