scholarly journals A software-radio front-end for microwave applications

2003 ◽  
Vol 1 ◽  
pp. 201-205
Author(s):  
M. Streifinger ◽  
T. Müller ◽  
J.-F. Luy ◽  
E. M. Biebl
Keyword(s):  
Signal To Noise Ratio ◽  
Schottky Diodes ◽  
Sampling Rate ◽  
Software Radio ◽  
Sampling Technique ◽  
Wide Band ◽  
Sigma Delta ◽  
Direct Sampling ◽  
Band Limited ◽  
Sigma Delta Adc

Abstract. In modern communication, sensor and signal processing systems digitisation methods are gaining importance. They allow for building software configurable systems and provide better stability and reproducibility. Moreover digital front-ends cover a wider range of applications and have better performance compared with analog ones. The quest for new architectures in radio frequency front-ends is a clear consequence of the ever increasing number of different standards and the resulting task to provide a platform which covers as many standards as possible. At microwave frequencies, in particular at frequencies beyond 10 GHz, no direct sampling receivers are available yet. A look at the roadmap of the development of commercial analog-to-digital-converters (ADC) shows clearly, that they can neither be expected in near future. We present a novel architecture, which is capable of direct sampling of band-limited signals at frequencies beyond 10 GHz by means of an over-sampling technique. The wellknown Nyquist criterion states that wide-band digitisation of an RF-signal with a maximum frequency ƒ requires a minimum sampling rate of 2 · ƒ . But for a band-limited signal of bandwidth B the demands for the minimum sampling rate of the ADC relax to the value 2 · B. Employing a noise-forming sigma-delta ADC architecture even with a 1-bit-ADC a signal-to-noise ratio sufficient for many applications can be achieved. The key component of this architecture is the sample-and-hold switch. The required bandwidth of this switch must be well above 2 · ƒ . We designed, fabricated and characterized a preliminary demonstrator for the ISM-band at 2.4 GHz employing silicon Schottky diodes as a switch and SiGe-based MMICs as impedance transformers and comparators. Simulated and measured results will be presented.

Design of Third-Order Single-Loop Full Feed-Forward Sigma Delta Modulator

2014 ◽  
Vol 609-610 ◽  
pp. 1176-1180
Author(s):  
Liang Liu ◽  
Song Chen ◽  
Chong He ◽  
Liang Yin ◽  
Xiao Wei Liu
Keyword(s):  
Model Building ◽  
Inertial Sensors ◽  
Sampling Rate ◽  
Third Order ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Feed Forward ◽  
Single Loop ◽  
Local Feedback ◽  
Sigma Delta Adc

Sigma Delta modulator is widely used in ADC for kinds of micro inertial sensors, Sigma Delta ADC can be easily integrated with digital circuits. It possesses some performances of good linearity and high accuracy, while it has no such strict requirements for the match of device dimensions. In this paper, the design of third-order Sigma Delta modulator with a structure of single-loop full feed-forward is accomplished, meanwhile it uses local feedback for zero optimization to improve the shaping capacity of the modulator noise within the signal bandwidth. The OSR (over-sampling rate) of the modulator is 128 and the signal bandwidth is 10 kHz. By the system model building and simulation in the Simulink of MATALAB, the SNR is 96.3 dB and the ENOB is 15.71 bits. Then the modulator is implemented into transistor-level circuits with 0.5um process, by the simulation in Spectre of Cadence, the SNR is 88.5 dB and the ENOB is 14.41 bits. 搜

VCO-BASED CONTINUOUS-TIME SIGMA DELTA ADC BASED ON A DUAL-VCO-QUANTIZER-LOOP STRUCTURE

2013 ◽  
Vol 22 (09) ◽  
pp. 1340013 ◽  
Author(s):  
Z. T. XU ◽  
X. L. ZHANG ◽  
J. Z. CHEN ◽  
S. G. HU ◽  
Q. YU ◽  
...  
Keyword(s):  
Continuous Time ◽  
Signal To Noise Ratio ◽  
Quantization Noise ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Loop Structure ◽  
Signal To Noise ◽  
Sigma Delta ◽  
Analog To Digital ◽  
Sigma Delta Adc

This paper explores a continuous time (CT) sigma delta (ΣΔ) analog-to-digital converter (ADC) based on a dual-voltage-controlled oscillator (VCO)-quantizer-loop structure. A third-order filter is adopted to reduce quantization noise and VCO nonlinearity. Even-order harmonics of VCO are significantly reduced by the proposed dual-VCO-quantizer-loop structure. The prototype with 10 MHz bandwidth and 400 MHz clock rate is designed using a 0.18 μm RF CMOS process. Simulation results show that the signal-to-noise ratio and signal-to-noise distortion ratio (SNDR) are 76.9 and 76 dB, respectively, consuming 37 mA at 1.8 V. The key module of the ADC, which is a 4-bit VCO-based quantizer, can convert the voltage signal into a frequency signal and quantize the corresponding frequency to thermometer codes at 400 MS/s.

scholarly journals A Novel Sigma-Delta Modulator with Fractional-Order Digital Loop Integrator

2017 ◽  
Vol 2017 ◽  
pp. 1-7
Author(s):  
Chi Xu ◽  
Yu Jin ◽  
Duli Yu
Keyword(s):  
Fractional Order ◽  
Analog Circuit ◽  
Dynamic Range ◽  
Signal To Noise Ratio ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Integer Order ◽  
Noise Characteristics ◽  
Chip Testing ◽  
Sigma Delta Adc

This paper proposes using a fractional-order digital loop integrator to improve the robust stability of Sigma-Delta modulator, thus extending the integer-order Sigma-Delta modulator to a non-integer-order (fractional-order) one in the Sigma-Delta ADC design field. The proposed fractional-order Sigma-Delta modulator has reasonable noise characteristics, dynamic range, and bandwidth; moreover the signal-to-noise ratio (SNR) is improved remarkably. In particular, a 2nd-order digital loop integrator and a digital PIλDμ controller are combined to work as the fractional-order digital loop integrator, which is realized using FPGA; this will reduce the ASIC analog circuit layout design and chip testing difficulties. The parameters of the proposed fractional-order Sigma-Delta modulator are tuned by using swarm intelligent algorithm, which offers opportunity to simplify the process of tuning parameters and further improve the noise performance. Simulation results are given and they demonstrate the efficiency of the proposed fractional-order Sigma-Delta modulator.

scholarly journals PROGRAMMABLE PARALLEL FBD SIGMA DELTA ADC RECONSTRUCTION STAGE DESIGN FOR SOFTWARE DEFINED RADIO RECEIVER

2016 ◽  
pp. 14-21
Author(s):  
Rihab Lahouli ◽  
Manel Ben-Romdhane ◽  
Chiheb Rebai ◽  
Dominique Dallet
Keyword(s):  
Software Defined Radio ◽  
Signal To Noise Ratio ◽  
Parallel Architecture ◽  
Use Case ◽  
Sigma Delta ◽  
Analog To Digital ◽  
Sigma Delta Modulators ◽  
Digital Reconstruction ◽  
Simulation Results ◽  
Sigma Delta Adc

Today’s bottleneck of signal processing in multistandard software defined radio (SDR) receiver is the analog-to-digital converter (ADC). Therefore, the authors present in this paper the design and simulation results of a programmable parallel frequency band decomposition (FBD) architecture for ADC. The designed parallel architecture is composed of six parallel branches based on discrete-time (DT) 4th order sigma delta modulators using single-bit quantizers. Each branch processes a sub-bandwidth of the received signal. Only needed branches are selected according to the chosen standard. The parallel sigma delta modulators’ outputs are handled by a demodulation-based digital reconstruction stage in order to provide the FBD sigma delta-based ADC output signal. The digital reconstruction stage differs from one communication standard to another. In this paper, its design is discussed for the UMTS use case. The objective is to propose a digital reconstruction design with optimized complexity. In fact, the authors propose a comparative study between some configurations of demodulation, decimation and filtering processes. Technical choices and simulation results are discussed. For UMTS use case, the proposed FBD sigma delta-based ADC architecture ensures a computed signal-to-noise ratio (SNR) over 74 dB.

scholarly journals A High-Dynamic-Range Switched-Capacitor Sigma-Delta ADC for Digital Micromechanical Vibration Gyroscopes

Micromachines ◽  
2018 ◽  
Vol 9 (8) ◽  
pp. 372 ◽  
Author(s):  
Risheng Lv ◽  
Weiping Chen ◽  
Xiaowei Liu
Keyword(s):  
Dynamic Range ◽  
Signal To Noise Ratio ◽  
High Dynamic Range ◽  
Cmos Technology ◽  
Noise Cancellation ◽  
Switched Capacitor ◽  
Noise Shaping ◽  
Sigma Delta ◽  
Multi Stage ◽  
Sigma Delta Adc

This paper presents a multi-stage noise shaping (MASH) switched-capacitor (SC) sigma-delta (ΣΔ) analog-to-digital converter (ADC) composed of an analog modulator with an on-chip noise cancellation logic and a reconfigurable digital decimator for MEMS digital gyroscope applications. A MASH 2-1-1 structure is employed to guarantee an absolutely stable modulation system. Based on the over-sampling and noise-shaping techniques, the core modulator architecture is a cascade of three single-loop stages containing feedback paths for systematic optimization to avoid deterioration in conversion accuracy caused by capacitor mismatch. A digital noise cancellation logic is also included to eliminate residual quantization errors in the former two stages, and those in the last stage are shaped by a fourth-order modulation. A multi-rate decimator follows the analog modulator to suit variable gyroscope bandwidth. Manufactured in a standard 0.35 μm CMOS technology, the whole chip occupies an area of 3.8 mm2. Experimental results show a maximum signal-to-noise ratio (SNR) of 100.2 dB and an overall dynamic range (DR) of 107.6 dB, with a power consumption of 3.2 mW from a 5 V supply. This corresponds to a state-of-the-art figure-of-merit (FoM) of 165.6 dB.

Design of a Digital Decimation Filter for High-Precision 4-Order Sigma-Delta ADC

2012 ◽  
Vol 503 ◽  
pp. 415-419 ◽  
Author(s):  
Wei Ping Chen ◽  
Qiang Fu ◽  
Xiao Wei Liu ◽  
Yan Xiao ◽  
Bin Zhang ◽  
...  
Keyword(s):  
High Precision ◽  
Sampling Rate ◽  
Stop Band ◽  
Cutoff Frequency ◽  
Pass Band ◽  
Sigma Delta ◽  
Band Filter ◽  
Cic Filter ◽  
Decimation Filter ◽  
Sigma Delta Adc

In this paper, a design of a digital decimation filter which has a output of 24 bits for high-precision 4-ordes Σ-Δ ADC is proposed. The digital decimation filter includes a CIC filter, a compensation filter and a half band filter. The over-sampling rate of the digital decimation filter is 256, the cutoff frequency is 1kHz, the coefficient of the pass-band ripple is -0.25dB, the stop-band attenuation is -162dB, simulation results using Matlab and modelsim are correct, the result of the FPGA verification shows that the design meet the requirement of the high-precision 4-ordes Σ-Δ ADC.

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