scholarly journals PROGRAMMABLE PARALLEL FBD SIGMA DELTA ADC RECONSTRUCTION STAGE DESIGN FOR SOFTWARE DEFINED RADIO RECEIVER

2016 ◽  
pp. 14-21
Author(s):  
Rihab Lahouli ◽  
Manel Ben-Romdhane ◽  
Chiheb Rebai ◽  
Dominique Dallet
Keyword(s):  
Software Defined Radio ◽  
Signal To Noise Ratio ◽  
Parallel Architecture ◽  
Use Case ◽  
Sigma Delta ◽  
Analog To Digital ◽  
Sigma Delta Modulators ◽  
Digital Reconstruction ◽  
Simulation Results ◽  
Sigma Delta Adc

Today’s bottleneck of signal processing in multistandard software defined radio (SDR) receiver is the analog-to-digital converter (ADC). Therefore, the authors present in this paper the design and simulation results of a programmable parallel frequency band decomposition (FBD) architecture for ADC. The designed parallel architecture is composed of six parallel branches based on discrete-time (DT) 4th order sigma delta modulators using single-bit quantizers. Each branch processes a sub-bandwidth of the received signal. Only needed branches are selected according to the chosen standard. The parallel sigma delta modulators’ outputs are handled by a demodulation-based digital reconstruction stage in order to provide the FBD sigma delta-based ADC output signal. The digital reconstruction stage differs from one communication standard to another. In this paper, its design is discussed for the UMTS use case. The objective is to propose a digital reconstruction design with optimized complexity. In fact, the authors propose a comparative study between some configurations of demodulation, decimation and filtering processes. Technical choices and simulation results are discussed. For UMTS use case, the proposed FBD sigma delta-based ADC architecture ensures a computed signal-to-noise ratio (SNR) over 74 dB.

VCO-BASED CONTINUOUS-TIME SIGMA DELTA ADC BASED ON A DUAL-VCO-QUANTIZER-LOOP STRUCTURE

2013 ◽  
Vol 22 (09) ◽  
pp. 1340013 ◽  
Author(s):  
Z. T. XU ◽  
X. L. ZHANG ◽  
J. Z. CHEN ◽  
S. G. HU ◽  
Q. YU ◽  
...  
Keyword(s):  
Continuous Time ◽  
Signal To Noise Ratio ◽  
Quantization Noise ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Loop Structure ◽  
Signal To Noise ◽  
Sigma Delta ◽  
Analog To Digital ◽  
Sigma Delta Adc

This paper explores a continuous time (CT) sigma delta (ΣΔ) analog-to-digital converter (ADC) based on a dual-voltage-controlled oscillator (VCO)-quantizer-loop structure. A third-order filter is adopted to reduce quantization noise and VCO nonlinearity. Even-order harmonics of VCO are significantly reduced by the proposed dual-VCO-quantizer-loop structure. The prototype with 10 MHz bandwidth and 400 MHz clock rate is designed using a 0.18 μm RF CMOS process. Simulation results show that the signal-to-noise ratio and signal-to-noise distortion ratio (SNDR) are 76.9 and 76 dB, respectively, consuming 37 mA at 1.8 V. The key module of the ADC, which is a 4-bit VCO-based quantizer, can convert the voltage signal into a frequency signal and quantize the corresponding frequency to thermometer codes at 400 MS/s.

NONLINEAR DYNAMICS OF A CLASS OF ANALOG-TO-DIGITAL CONVERTERS

1992 ◽  
Vol 02 (02) ◽  
pp. 325-340 ◽  
Author(s):  
ORLA FEELY ◽  
LEON O. CHUA
Keyword(s):  
Region Of Interest ◽  
Self Similarity ◽  
Globally Asymptotically Stable ◽  
Sigma Delta ◽  
Analog To Digital ◽  
Sigma Delta Modulators ◽  
Stable Periodic ◽  
The One ◽  
Almost All ◽  
Constant Slope

Oversampled sigma-delta modulators are finding widespread use in audio and other signal processing applications, due to their simple structure and robustness to circuit imperfections. Exact analyses of the system are complicated by the presence of a discontinuous nonlinear element—a one-bit quantizer. In this paper, we study the dynamics of the one-dimensional mapping which models the behavior of the single-loop modulator. This mapping has a discontinuity at the origin and constant slope at all other points. With slope one, the dynamics in the region of interest reduce to those of the rotation of the circle. With slope less than one, almost all system inputs give rise to globally asymptotically stable periodic orbits. We emphasize the case with slope greater than one, and explain the structure of the resultant bifurcation diagram. A symbolic dynamics based study allows us to explain the self-similarity of the dynamics and the nature of chaos in the system.

scholarly journals Optimized System Level Hardware Realization of Built-in-Self-Test Approach for Sigma-Delta Analog-to-Digital Converter

2016 ◽  
Vol 4 (3) ◽  
pp. 85-90
Author(s):  
Anil Kumar Sahu ◽  
Vivek Kumar Chandra ◽  
G R Sinha
Keyword(s):  
System Level ◽  
Dynamic Parameters ◽  
Analog To Digital Converter ◽  
Digital Converter ◽  
Sigma Delta ◽  
Matlab Simulink ◽  
Analog To Digital ◽  
System Level Modeling ◽  
Self Test ◽  
Sigma Delta Adc

System-level modeling is generally needed due to simultaneous increase in design complexity with multi-million gate designs in today’s system-on-chips (SoCs). System C is generally applied to system-level modeling of Sigma-Delta ADC. CORDIC technique and test generation for the testing of mixed signal circuit components such as analog-to-digital converter is mostly implemented in system level modeling. This work focuses on developing fast and yet accurate model of BIST approach for Sigma-Delta ADC. The Sigma-Delta modulator’s ADC static parameters as well as dynamic parameters are degraded. One of the dynamic parameters, signal-to-noise ratio (SNR) is directly obtained by the SIMSIDES (MATLAB SIMULINK tool). Then, the obtained parameters are tested by using Built-in-self-test that is desirable for the VLSI system in order to reduce the non-recurring cost (NRE) per chip by the manufacturer. This paper demonstrates a possibility to realize a simulation of testing strategy of high-resolution Sigma-Delta modulator using MATLAB SIMULINK and Xilinx EDA tool environment. This work also contributes towards the Output Response Analyzer (ORA) being used for testing parameters which help in reducing the difficulties in design of the complete ORA circuit. Moreover, the reusable features of hardware in the computation of different parameters are also improved in the ORA design.

A triple-channel incremental zoom-ADC for 3-DoF MEMS digital gyroscopes

2020 ◽  
Vol 34 (13) ◽  
pp. 2050136
Author(s):  
Risheng Lv ◽  
Weiping Chen ◽  
Qiang Fu ◽  
Liang Yin ◽  
Yufeng Zhang ◽  
...  
Keyword(s):  
Noise Suppression ◽  
Signal To Noise Ratio ◽  
Cmos Technology ◽  
Hybrid Architecture ◽  
Dynamic Element Matching ◽  
Loop Filter ◽  
Sigma Delta ◽  
Analog To Digital ◽  
Synchronous Sampling ◽  
On Chip

This paper presents a multiplexed analog-to-digital converter (ADC) consisting mainly of high-precision sampling holders (S/H) and an incremental zoom ADC. Flip-around design is employed in S/H modules for power economy and noise suppression. Based on efficient coordination between S/H and multiplexers, synchronous sampling is available in the whole triple-channel ADC to maintain phase accordance. The core converter employed a hybrid architecture of successive approximation register (SAR) and Sigma-Delta [Formula: see text], which constitutes an energy-efficient zoom ADC. Final conversion result is a combination of the two steps. Both the SAR and [Formula: see text] modulation share a third-order loop filter to compromise between systematic stability and input range. On-chip digital logic include capacitor array controlling and dynamic-element-matching (DEM) technique. Manufactured in a standard [Formula: see text]m CMOS technology, the whole chip occupies an area of 2.7 mm2. Experimental results show a maximum signal-to-noise ratio (SNR) of 100.2 dB, with a power consumption of 2.1 mW from a 5 V supply.

The Design of the Integrator of Sigma-Delta Modulator

2013 ◽  
Vol 562-565 ◽  
pp. 477-481
Author(s):  
Xiao Wei Liu ◽  
Song Chen ◽  
Liang Liu ◽  
Jian Yang ◽  
Wei Ping Chen
Keyword(s):  
Low Frequency ◽  
Clock Signal ◽  
Gain Bandwidth ◽  
Two Phase ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Fully Differential ◽  
Unity Gain ◽  
Simulation Results ◽  
Sigma Delta Adc

A kind of fully differential integrator is designed for the modulator of Sigma-delta ADC in this paper. Fully differential structure is adopted to enlarge the amplitude of output, restrain nonlinearity and increase competence of anti-interference. The frequency of signal in this design is 10kHz and the frequency of clock signal is 100kHz. The design of fully differential integrator, capacitive common mode feedback, two-phase unoverlapping clock and switched capacitor integrator are accomplished in this paper. The simulation results in Cadence using 0.5um process show that the low-frequency gain of operational amplifier is 69.87dB, unity gain bandwidth is 37.74MHz, phase margin is 67.73 degrees and slew rate is more than 31V/μs.

Testing of High-Resolution Analog-to-Digital Converters Using Segmentation and Optimized Low-Precision DAC

2013 ◽  
Vol 333-335 ◽  
pp. 1669-1672
Author(s):  
Cheng Huang ◽  
You Hui Li ◽  
Ya Dan Zhang ◽  
Nan Wang
Keyword(s):  
High Resolution ◽  
Signal Source ◽  
Huge Number ◽  
Histogram Method ◽  
Sigma Delta ◽  
New Approach ◽  
Analog To Digital ◽  
Adc Test ◽  
Sigma Delta Adc ◽  
Adc Testing

The main challenges of high-resolution ADC testing are the huge number of samples and the expensive test equipment, especially the requirement of high linearity signal source. In this paper, the scaling and segmentation algorithm which combines SEIR with windows is introduced for high-resolution ADC test. The new approach is validated by simulation with a 24-bit sigma-delta ADC. INL error of the proposed method is ±0.2LSB, which is less than the SEIR method of ±0.5LSB,and less than the histogram method of ±0.3LSB. About 20 million samples are required in the proposed method, which is about 30 times less than the traditional histogram method.

scholarly journals A Novel Sigma-Delta Modulator with Fractional-Order Digital Loop Integrator

2017 ◽  
Vol 2017 ◽  
pp. 1-7
Author(s):  
Chi Xu ◽  
Yu Jin ◽  
Duli Yu
Keyword(s):  
Fractional Order ◽  
Analog Circuit ◽  
Dynamic Range ◽  
Signal To Noise Ratio ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
Integer Order ◽  
Noise Characteristics ◽  
Chip Testing ◽  
Sigma Delta Adc

This paper proposes using a fractional-order digital loop integrator to improve the robust stability of Sigma-Delta modulator, thus extending the integer-order Sigma-Delta modulator to a non-integer-order (fractional-order) one in the Sigma-Delta ADC design field. The proposed fractional-order Sigma-Delta modulator has reasonable noise characteristics, dynamic range, and bandwidth; moreover the signal-to-noise ratio (SNR) is improved remarkably. In particular, a 2nd-order digital loop integrator and a digital PIλDμ controller are combined to work as the fractional-order digital loop integrator, which is realized using FPGA; this will reduce the ASIC analog circuit layout design and chip testing difficulties. The parameters of the proposed fractional-order Sigma-Delta modulator are tuned by using swarm intelligent algorithm, which offers opportunity to simplify the process of tuning parameters and further improve the noise performance. Simulation results are given and they demonstrate the efficiency of the proposed fractional-order Sigma-Delta modulator.

scholarly journals Phase locked loop-based clock synthesizer for reconfigurable analog-to-digital converters

2021 ◽  
Author(s):  
Mateus B. Castro ◽  
Raphael R. N. Souza ◽  
Agord M. P. Junior ◽  
Eduardo R. Lima ◽  
Leandro T. Manera
Keyword(s):  
Supply Voltage ◽  
Signal To Noise Ratio ◽  
Phase Locked Loop ◽  
Analog To Digital Converters ◽  
Cmos Process ◽  
Reference Frequency ◽  
Process Technology ◽  
Worst Case ◽  
Sigma Delta ◽  
Analog To Digital

AbstractThis paper presents the complete design of a phase locked loop-based clock synthesizer for reconfigurable analog-to-digital converters. The synthesizer was implemented in TSMC 65 nm CMOS process technology and the presented results were obtained from extracted layout view with parasitics. The synthesizer generates clock frequencies ranging from 40 to 230 MHz considering a reference frequency of 10 MHz and a supply voltage of 1.2 V. Worst case current consumption is 634 $$\mu $$ μ W, settling time is 6 $$\mu $$ μ s, maximum jitter is 1.3 ns in a 0.037 mm$$^2$$ 2 area. Performance was validated in a test $$\Sigma \Delta $$ Σ Δ Modulator with bandwidths of 200 kHz, 500 kHz and 2 MHz, and oversampling frequencies of 40, 60 and 80 MHz respectively, with negligible signal-to-noise ratio degradation compared to an ideal clock.

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