scholarly journals A 3rd-order current-mode filter in 0.12 μm CMOS

2008 ◽  
Vol 6 ◽  
pp. 201-204 ◽  
Author(s):  
R. Kolm ◽  
H. Zimmermann
Keyword(s):  
Dynamic Range ◽  
Software Radio ◽  
Current Mode ◽  
Current Steering ◽  
Butterworth Filter ◽  
Current Consumption ◽  
Noise Density ◽  
Current Steering Dac ◽  
A Current

Abstract. For software radio applications in system-on-chips, a 3rd-order current-mode Butterworth filter in 120 nm CMOS is realized. This filter is used for reconstruction purposes between a current-steering DAC and a current-mode mixer. Power can be reduced by using a current-mode architecture. The cut-off frequency of this filter is switchable between 1 MHz and 4 MHz, the current consumption is 4.5 mA at VDD=1.5 V, the inband noise density is 100 pA/√Hz and it has a dynamic range up to 65 dB.

Synthesis for Butterworth Filter Using Compact VDTA Based on Sallen- Key Topology

2020 ◽  
Vol 13 (5) ◽  
pp. 681-688
Author(s):  
Yong-An Li
Keyword(s):  
Network Theory ◽  
Current Mode ◽  
Second Order ◽  
Frequency Filter ◽  
Butterworth Filter ◽  
Admittance Matrix ◽  
Floating Capacitor ◽  
A Current

Background: The original filter including grounded or virtual ground capacitors can be synthesized by using the NAM expansion. However, so far the filters including floating capacitor, such as Sallen-Key filter, have not been synthesized by means of the NAM expansion. This is a problem to be researched further. Methods: By using the adjoint network theory, the Sallen-Key filter including floating capacitor first is turned into a current-mode one, which includes a grounded capacitor and a virtual ground capacitor. Then the node admittance matrix, after derived, is extended by using NAM expansion. Results: At last, one VDTA Sallen-Key filter is received. It employs single compact VDTA and two grounded capacitors. Conclusion: A Butterworth VDTA second-order frequency filter based on Sallen-Key topology with fo = 100kHz, HLP = -HBP=1, is designed.

A 12-BIT 400-MS/s CURRENT-STEERING DAC WITH DEGLITCHING TECHNIQUE

2014 ◽  
Vol 23 (01) ◽  
pp. 1450004 ◽  
Author(s):  
XIAOBO XUE ◽  
XIAOLEI ZHU ◽  
QIFENG SHI ◽  
LENIAN HE
Keyword(s):  
Dynamic Range ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Signal Frequency ◽  
Current Steering ◽  
Digital To Analog Converter ◽  
Measurement Results ◽  
Voltage Swing ◽  
Current Steering Dac ◽  
Low Supply Voltage

In this paper, a 12-bit current-steering digital-to-analog converter (DAC) employing a deglitching technique is proposed. The deglitching technique is realized by lowering the voltage swing of the control signal as well as by using a method of glitch counteraction (GC). A new switch–driver structure is designed to enable the effectiveness of the GC and provide sufficient driving capability under a low supply voltage. Moreover, the control signal's rise/fall asymmetry which increases the glitch error can be suppressed by using the proposed switch–driver structure. The 12-bit DAC is implemented in 180 nm CMOS technology. The measurement results show that the spurious free dynamic range (SFDR) at low signal frequency is 78.8 dB, and it is higher than 70 dB up to 60 MHz signal frequency at 400 MS/s. The measured INL and DNL are both less than ±0.6 LSB.

scholarly journals Design and implementation of 4 bit binary weighted current steering DAC

2020 ◽  
Vol 10 (6) ◽  
pp. 5642
Author(s):  
Jayeshkumar J. Patel ◽  
Amisha P. Naik
Keyword(s):  
Supply Voltage ◽  
Biomedical Application ◽  
Current Mode ◽  
Cmos Technology ◽  
Current Steering ◽  
Digital To Analog Converter ◽  
Transmission Gate ◽  
Linearity Error ◽  
Current Steering Dac ◽  
Binary Weighted

A compact current-mode Digital-to-Analog converter (DAC) suitable for biomedical application is repesented in this paper .The designed DAC is binary weighted in 180nm CMOS technology with 1.8V supply voltage. In this implementation, authors have focused on calculaton of Non linearity error say INL and DNL for 4 bit DAC having various type of switches: NMOS, PMOS and Transmission Gate. The implemented DAC uses lower area and power compared to unary architecture due to absence of digital decoders. The desired value of Integrated non linearity (INL) and Differential non linearity (DNL) for DAC for are within a range of +0.5LSB. Result obtained in this works for INL and DNL for the case DAC using Transmission Gate is +0.34LSB and +0.38 LSB respectively with 22mW power dissipation.

scholarly journals A Current-Steering DAC Architecture with Novel Switching Scheme for GPON Burst-Mode Laser Drivers

2007 ◽  
Vol E90-C (4) ◽  
pp. 877-884 ◽  
Author(s):  
W. CHEN ◽  
J. BAUWELINCK ◽  
P. OSSIEUR ◽  
X.-Z. QIU ◽  
J. VANDEWEGE
Keyword(s):  
Current Steering ◽  
Switching Scheme ◽  
Mode Laser ◽  
Burst Mode ◽  
Laser Drivers ◽  
Current Steering Dac ◽  
A Current

A 12-bit 200-MHz CURRENT-STEERING DAC WITH CALIBRATION

2014 ◽  
Vol 23 (04) ◽  
pp. 1450053 ◽  
Author(s):  
FAN XIA ◽  
YIQIANG ZHAO ◽  
GONGYUAN ZHAO
Keyword(s):  
Dynamic Range ◽  
Current Source ◽  
Cmos Technology ◽  
Signal Frequency ◽  
Current Steering ◽  
Digital To Analog Converter ◽  
Differential Nonlinearity ◽  
Spurious Free Dynamic Range ◽  
Source Block ◽  
Current Steering Dac

In this paper, a 12-bit current-steering digital-to-analog converter (DAC) with high static and dynamic linearity is proposed. Compared to traditional intrinsic-accuracy DACs, the static linearity is obtained by a series of subsidiary DACs which can shorten the calibration cycle with smaller additional circuits. The presented DAC is based on the segmented architecture and layout has been carefully designed so that better synchronization among the current sources can be achieved. The DAC is implemented in a standard 0.18-μm CMOS technology and the current source block occupies less than 0.5 mm2. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) performance is ± 0.3 LSB and ± 0.5 LSB, respectively, and the spurious free dynamic range (SFDR) is 75 dB at 1 MHz signal frequency and 200 MHz sampling frequency.

CDBA based current instrumentation amplifier

2016 ◽  
Vol 4 ◽  
pp. 11 ◽  
Author(s):  
Priyanka Gupta ◽  
Kunal Gupta ◽  
Neeta Pandey ◽  
Rajeshwari Pandey
Keyword(s):  
Current Mode ◽  
Instrumentation Amplifier ◽  
Pspice Simulations ◽  
Differential Gain ◽  
Novel Method ◽  
Current Difference ◽  
A Current

This paper presents a novel method to realize a current mode instrumentation amplifier (CMIA) through CDBA (Current difference Buffered Amplifier). It employs two CDBAs and two resistors to obtain desired functionality. Further, it does not require any resistor matching. The gain can be set according to the resistor values. It offers high differential gain and a bandwidth, which is independent of gain. The working of the circuit is verified through PSPICE simulations using CFOA IC based CDBA realization.

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