DETECTING THE FAILURE LOCATION IN A 10 KV ELECTRICAL NETWORK WITH A THREE-WINDING FEEDING TRANSFORMER UNDER CONDITION OF A METALIC FAULT AND DUE TO THE TRANSITION RESISTANCE FAULT WHEN MEASURED AT THE BEGINNING AND AT THE END OF THE LINE

Abstract A systemic analysis was chosen to evaluate a real case Bluetooth (BT) radio failure in the aspects of RF communication, digital design, firmware, application software, semiconductor device physics and processing, and failure analysis. This paper explores the range of testing, including customer application testing, required to confirm and localize a BT RF communication failure. It shows that the radio communication failure was not, as expected, caused by faulty radio hardware; it was rather linked to problematic encryption hardware at the assistance of the Synergy BT to mobile application. The paper also explores that the digital fault can only be detected by the timing sensitive transition fault scan patterns and how to obtain the physical failure location. Thus, the combination of ATPG and application testing provides a consistency between electrical diagnostics which yields a higher success rate at subsequent physical failure analysis of complex modern RF System on a Chip.

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A Silicon Debugging Methodology on Customer Prototype for Wafer Foundries

ISTFA 2012: Conference Proceedings from the 38th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2012p0411 ◽

2012 ◽

Author(s):

Mai Zhihong ◽

Ng Tsu Hau ◽

Dawood M. Khalid ◽

Tan Pik Kee ◽

Jeffrey Lam

Keyword(s):

Case Studies ◽

Semiconductor Industry ◽

Full Information ◽

Limited Information ◽

Ip Protection ◽

First Case ◽

Silicon Debugging ◽

Failure Location ◽

Device Chip ◽

Latch Up

Abstract IP protection is of major importance for a semiconductor company and only limited information is made available for device debugging for the product outsourced to a foundry. In order to position ourselves better in the ever competitive semiconductor industry, with the consideration of IP protection, we have to provide the customers with the Si debugging capability and device/chip verification services in foundry. This paper explores the Si debugging methodology and technique in a foundry. Two case studies are presented and discussed. The first case illustrates the isolation of the failure location by InGaAs microscopy, upon which the failure was identified to be caused by a latch-up issue. In the second case, due to confidentiality considerations from the customer, full information could not be provided to the foundry for silicon debugging. The paper illustrates the ability to effectively debug a failure despite being constrained by limited information from the customer.

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The Use of TMAH to Etch Silicon and Expose Metal Bridging Failures

ISTFA 2000: Conference Proceedings from the 26th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2000p0231 ◽

2000 ◽

Author(s):

Mark Morris ◽

James Mohr ◽

Esteban Ortiz ◽

Steven Englebretson

Keyword(s):

Failure Mechanism ◽

Schottky Diodes ◽

Tetramethylammonium Hydroxide ◽

Novel Approach ◽

Failure Location ◽

Metal Etching ◽

Plastic Mold

Abstract Determination of metal bridging failures on plastic encapsulated devices is difficult due to the metal etching effects that occur while removing many of the plastic mold compounds. Typically, the acids used to remove the encapsulation are corrosive to the metals that are found within the device. Thus, decapsulation can result in removal of the failure mechanism. Mechanical techniques are often not successful due to damage that results in destruction of the die and failure mechanism. This paper discusses a novel approach to these types of failures using a silicon etch and a backside evaluation. The desirable characteristics of the technique would be to remove the silicon and leave typical device metals unaffected. It would also be preferable that the device passivation and oxides not be etched so that the failure location is not disturbed. The use of Tetramethylammonium Hydroxide (TMAH), was found to fit these prerequisites. The technique was tested on clip attached Schottky diodes that exhibited resistive shorting. The use of the TMAH technique was successful at exposing thin solder bridges that extruded over the edge of the die resulting in failure.

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Pseudo-Dynamic Fault Isolation Technique Using Backside Emission Microscopy – Case Study, Where All Other Methods Fail

ISTFA 2002: Conference Proceedings from the 28th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2002p0539 ◽

2002 ◽

Author(s):

Yoav Weizman ◽

Ezra Baruch ◽

Michael Zimin

Keyword(s):

Failure Analysis ◽

Process Variations ◽

Fault Isolation ◽

Operating Conditions ◽

Detection Sensitivity ◽

Isolation Technique ◽

Root Cause ◽

Emission Microscopy ◽

Failure Location ◽

Noisy Background

Abstract Emission microscopy is usually implemented for static operating conditions of the DUT. Under dynamic operation it is nearly impossible to identify a failure out of the noisy background. In this paper we describe a simple technique that could be used in cases where the temporal location of the failure was identified however the physical location is not known or partially known. The technique was originally introduced to investigate IDDq failures (1) in order to investigate timing related issues with automated tester equipment. Ishii et al (2) improved the technique and coupled an emission microscope to the tester for functional failure analysis of DRAMs and logic LSIs. Using consecutive step-by-step tester halting coupled to a sensitive emission microscope, one is able detect the failure while it occurs. We will describe a failure analysis case in which marginal design and process variations combined to create contention at certain logic states. Since the failure occurred arbitrarily, the use of the traditional LVP, that requires a stable failure, misled the analysts. Furthermore, even if we used advanced tools as PICA, which was actually designed to locate such failures, we believe that there would have been little chance of observing the failure since the failure appeared only below 1.3V where the PICA tool has diminished photon detection sensitivity. For this case the step-by-step halting technique helped to isolate the failure location after a short round of measurements. With the use of logic simulations, the root cause of the failure was clear once the failing gate was known.

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