Localization of a Complex Failure by Combining ATPG and Customer-Oriented Application Testing

2013 ◽  
Author(s):  
Kai Wang ◽  
Rhys Weaver ◽  
David Johnson
Keyword(s):  
Failure Analysis ◽  
Semiconductor Device ◽  
Digital Design ◽  
Radio Communication ◽  
Communication Failure ◽  
Systemic Analysis ◽  
Rf Communication ◽  
System On A Chip ◽  
Electrical Diagnostics ◽  
Failure Location

Abstract A systemic analysis was chosen to evaluate a real case Bluetooth (BT) radio failure in the aspects of RF communication, digital design, firmware, application software, semiconductor device physics and processing, and failure analysis. This paper explores the range of testing, including customer application testing, required to confirm and localize a BT RF communication failure. It shows that the radio communication failure was not, as expected, caused by faulty radio hardware; it was rather linked to problematic encryption hardware at the assistance of the Synergy BT to mobile application. The paper also explores that the digital fault can only be detected by the timing sensitive transition fault scan patterns and how to obtain the physical failure location. Thus, the combination of ATPG and application testing provides a consistency between electrical diagnostics which yields a higher success rate at subsequent physical failure analysis of complex modern RF System on a Chip.

Pseudo-Dynamic Fault Isolation Technique Using Backside Emission Microscopy – Case Study, Where All Other Methods Fail

2002 ◽  
Author(s):  
Yoav Weizman ◽  
Ezra Baruch ◽  
Michael Zimin
Keyword(s):  
Failure Analysis ◽  
Process Variations ◽  
Fault Isolation ◽  
Operating Conditions ◽  
Detection Sensitivity ◽  
Isolation Technique ◽  
Root Cause ◽  
Emission Microscopy ◽  
Failure Location ◽  
Noisy Background

Abstract Emission microscopy is usually implemented for static operating conditions of the DUT. Under dynamic operation it is nearly impossible to identify a failure out of the noisy background. In this paper we describe a simple technique that could be used in cases where the temporal location of the failure was identified however the physical location is not known or partially known. The technique was originally introduced to investigate IDDq failures (1) in order to investigate timing related issues with automated tester equipment. Ishii et al (2) improved the technique and coupled an emission microscope to the tester for functional failure analysis of DRAMs and logic LSIs. Using consecutive step-by-step tester halting coupled to a sensitive emission microscope, one is able detect the failure while it occurs. We will describe a failure analysis case in which marginal design and process variations combined to create contention at certain logic states. Since the failure occurred arbitrarily, the use of the traditional LVP, that requires a stable failure, misled the analysts. Furthermore, even if we used advanced tools as PICA, which was actually designed to locate such failures, we believe that there would have been little chance of observing the failure since the failure appeared only below 1.3V where the PICA tool has diminished photon detection sensitivity. For this case the step-by-step halting technique helped to isolate the failure location after a short round of measurements. With the use of logic simulations, the root cause of the failure was clear once the failing gate was known.

Single Die 'Hands-Free' Layer-by-Layer Mechanical Deprocessing for Failure Analysis or Reverse Engineering

2008 ◽  
Author(s):  
Tony Moor ◽  
Eli Malyanker ◽  
Efrat Raz-Moyal
Keyword(s):  
Reverse Engineering ◽  
Failure Analysis ◽  
Competitive Analysis ◽  
Patent Protection ◽  
Semiconductor Device ◽  
Mechanical Polishing ◽  
Layer By Layer ◽  
Free Layer ◽  
Step Method ◽  
Computer Controlled

Abstract The idea behind Destructive Semiconductor Reverse Engineering (DSRE) is to investigate a device in part or as a whole using many of the techniques employed in the physical failure analysis (PFA) field. The device is usually examined for intellectual property/patent protection or competitive analysis purposes. This paper presents a technique for the full layer-by-layer deprocessing of a single semiconductor device using purely mechanical polishing for DSRE or FA. It describes a step-by-step method developed by Raw Science/Datel Design and Development and Gatan for the reliable, purely mechanical deprocessing of individual dice. The paper presents the two modifications made to the process to virtually eliminate the edge effects. A computer controlled mechanical polishing system coupled with a unique customized process allows for the investigation of those one of a kind samples as a whole with 100% success rate.

CF4-Free Microwave Induced Plasma Decapsulation of Automotive Semiconductor Devices

2016 ◽  
Author(s):  
Jiaqi Tang ◽  
Jing Wang ◽  
Gregory B. Anderson ◽  
Johannes Bruckmeier ◽  
Claudia Keller ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Semiconductor Device ◽  
Copper Wire ◽  
Semiconductor Devices ◽  
Etching Rate ◽  
Automatic Process ◽  
Microwave Induced Plasma ◽  
Bond Wires ◽  
Etching Selectivity ◽  
Bond Pads

Abstract Failure analysis of automotive semiconductor devices requires highly reliable techniques to guaranty the success of artifact-free decapsulation with high repeatability and reproducibility. With the introduction of new qualification standards, new mold compounds, and new packaging structures, advanced decapsulation tools are needed to enable failure analysis to achieve a high success rate. Microwave Induced Plasma (MIP) machine has been developed as an advanced decapsulation solution. The CF4-free MIP etching ensures artifact-free exposure of bond wires made of new materials, the die, passivation, bond pads, and original failure sites. The high mold compound etching rate, high etching selectivity of mold compound to wire/pad/passivation/die, and the fully automatic process are the unique features of MIP decapsulation. Comparisons are made between acid, conventional plasma with CF4, and CF4-free MIP decapsulation. Multiple case studies are discussed that address challenging automotive semiconductor device decapsulation, including bare copper wire, copper redistribution layer, exposed power copper metal, stitch bond on silver plated leadframe, complex mold compound, Bond-Over-Active-Circuit, eWLB, and localized decapsulation.

Time Domain Reflectometry as a Device Packaging Level Failure Analysis and Failure Localization Tool

2000 ◽  
Author(s):  
Damion T. Searls ◽  
Anura Don ◽  
Emilie Dy ◽  
Deepak Goyal
Keyword(s):  
Failure Analysis ◽  
Time Domain ◽  
Flip Chip ◽  
Low Voltage ◽  
Time Domain Reflectometry ◽  
Stress Tests ◽  
X Ray ◽  
Customer Returns ◽  
Failure Location ◽  
Electrical Connectivity

Abstract Detecting failure in electrical connectivity at the component packaging level is a major expenditure of the industry’s failure analysis (FA) resources. These package failures can result from material/manufacturing excursions, stress tests, and/or customer returns. However, many of the methods employed currently (such as X-ray or crosssectioning) can fall short in terms of throughput time, or success rate. Moreover, many FA techniques can be destructive and therefore leave the sample useless for subsequent tests. On the other hand, time domain reflectometry (TDR) can be used as a component packaging level FA tool which meets the needs of quickly, precisely, and non-destructively locating electrical connectivity problems in signal traces. Once the failure location has been pin pointed, other FA methods (X-ray, cross-section, etc.) can be used more easily to determine why the failure occurred. Since TDR testing involves no physical preparation, the sample will be completely intact for subsequent tests. TDR uses a low voltage, low current, and very short rise time voltage pulse to determine the impedance of a signal trace as a function of time. With a waveform of trace impedance versus time, not only can the presence of a failure be detected, but the distance along the trace to the anomaly can also be quickly determined. This paper presents TDR as a useful tool for package level failure analysis labs. The paper proposes one set of solutions for enabling effective TDR analysis (e.g., TDR test fixturing), and discusses some TDR methodologies for detecting and locating anomalies. The methodologies will be illustrated using three example cases that reflect some commonly used packaging technologies: Flip-Chip Organic Land Grid Array (FC-OLGA), Flip-Chip Pin Grid Array (FC-PGA), and Plastic Land Grid Array (PLGA).

A Novel Approach for Enhancing Critical FIB Imaging for Failure Analysis and Circuit Edit Applications

2004 ◽  
Author(s):  
Joseph Myers ◽  
Marsha Abramo ◽  
Michael Anderson ◽  
Michael W. Phaneuf
Keyword(s):  
Aspect Ratio ◽  
Failure Analysis ◽  
Secondary Electron ◽  
Semiconductor Device ◽  
Ion Beam ◽  
Sample Surface ◽  
Beam Current ◽  
Shielding Effect ◽  
Endpoint Detection ◽  
Novel Approach

Abstract As semiconductor device features continue to decrease in size from merely sub micron to below 100 nanometers it becomes necessary to mill smaller and higher aspect ratio FIB vias with reduced ion beam current. This significantly reduces the number of secondary electrons and ions available for endpoint detection and imaging. In addition FIB gas assisted etching introduces a gas delivery nozzle composed of conductive material. This component is grounded to prevent charge build up during ion beam imaging or milling. The proximity of the nozzle to the sample surface creates a shielding effect which reduces the secondary electron detection level as well [1]. The ability to enhance secondary electron imaging for end point detection is required for successful FIB circuit edit and failure analysis applications on advanced technologies. This paper reviews the results obtained using FIB Assist, an image and signal enhancement product for the FEI / Micrion platform, for critical FIB endpoint determination. Examples of FIB fabricated probe points with 30 x 30 nm FIB vias and circuit edit applications endpointing on metal 1 with high aspect ratio holes are presented.

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