An Area-Efficient Multi-Phase Fractional-Ratio Clock Frequency Multiplier

2016 ◽  
Vol 16 (1) ◽  
pp. 143-146 ◽  
Author(s):  
Sangwoo Han ◽  
Jongtae Lim ◽  
Jongsun Kim
Keyword(s):  
Frequency Multiplier ◽  
Clock Frequency ◽  
Multi Phase ◽  
Area Efficient

Energy-Efficient and Area-Efficient QC-LDPC with RS Decoders Using 2M-LMSA

2014 ◽  
Vol 24 (02) ◽  
pp. 1550026 ◽  
Author(s):  
Chang-Kun Yao ◽  
Yun-Ching Tang ◽  
Hongchin Lin
Keyword(s):  
Energy Efficient ◽  
Communication Systems ◽  
Average Power ◽  
Ldpc Code ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Hardware Complexity ◽  
Chip Area ◽  
Ldpc Decoder ◽  
Area Efficient

This study proposes an energy-efficient and area-efficient dual-path low-density parity-check (LDPC) with Reed–Solomon (RS) decoder for communication systems. Hardware complexity is reduced by applying a dual-path 2-bit modified layered min-sum algorithm (2M-LMSA) to a (2550, 2040) quasi-cyclic LDPC (QC-LDPC) code with the column and row weights of 3 and 15, respectively. The simplified check node units (CNUs) reduce memory and routing complexity as well as the energy needed to decode each bit. A throughput of 11 Gb/s is achieved by using 90-nm CMOS technology at a clock frequency of 208 MHz at 0.9 V with average power of 244 mW on a chip area of 3.05 mm2. Decoding performance is further improved by appending the (255, 239) RS decoder after the LDPC decoder. The LDPC plus RS decoder consumes the power of 434 mW on the area of 3.45 mm2.

A 250-Mb/s to 6-Gb/s Referenceless Clock and Data Recovery Circuit With Clock Frequency Multiplier

2017 ◽  
Vol 64 (6) ◽  
pp. 650-654 ◽  
Author(s):  
Ja-Young Kim ◽  
Junyoung Song ◽  
Jungtaek You ◽  
Sewook Hwang ◽  
Sang-Geun Bae ◽  
...  
Keyword(s):  
Clock And Data Recovery ◽  
Frequency Multiplier ◽  
Data Recovery ◽  
Clock Frequency

scholarly journals An efficient hardware implementation of a combinations generator

2017 ◽  
Vol 4 (20) ◽  
pp. 405-413
Author(s):  
Tomasz Mazurkiewicz
Keyword(s):  
Hardware Implementation ◽  
Fpga Implementation ◽  
Clock Frequency ◽  
Binary Vectors ◽  
Maximum Clock Frequency ◽  
Area Efficient

In this paper an area-efficient hardware implementation of a Bincombgen algorithm was presented. This algorithm generates all (n,k) combinations in the form of binary vectors. The generator was implemented using Verilog language and synthesized using Xilinx and Intel-Altera software. Some changes were applied to the original code, which allows our FPGA implementation to be more efficient than in the previously published papers. The usage of chip resources and maximum clock frequency for different values of n and k parameters are presented.

DESIGN OF AN AREA-EFFICIENT HIGH-THROUGHPUT SHIFT-BASED LDPC DECODER

2013 ◽  
Vol 22 (06) ◽  
pp. 1350039 ◽  
Author(s):  
Yun-Ching Tang ◽  
Hong-Ren Wang ◽  
Hongchin Lin ◽  
Jun-Zhe Huang
Keyword(s):  
High Throughput ◽  
Supply Voltage ◽  
Critical Path ◽  
Cmos Process ◽  
Path Delay ◽  
Clock Frequency ◽  
Storage Unit ◽  
Ldpc Decoder ◽  
Routing Congestion ◽  
Area Efficient

An area-efficient high-throughput shift-based LDPC decoder architecture is proposed. The specially designed (512, 1,024) parity-check matrix is effective for partial parallel decoding by the min-sum algorithm (MSA). To increase throughput during decoding, two data frames are fed into the decoder to minimize idle time of the check node unit (CNU) and the variable node unit (VNU). Thus, the throughput is increased to almost two-fold. Unlike the conventional architecture, the message storage unit contains shift registers instead of de-multiplexers and registers. Therefore, hardware costs are reduced. Routing congestion and critical path delay are also reduced, which increases energy efficiency. An implementation of the proposed decoder using TSMC 0.18 μm CMOS process achieves a decoding throughput of 1.725 Gbps, at a clock frequency of 56 MHz, a supply voltage of 1.8 V, and a core area of 5.18 mm2. The normalized area is smaller and the throughput per normalized power consumption is higher than those reported using the conventional architectures.

scholarly journals Area-efficient programmable arbiter for inter-layer communications in 3-D network-on-chip

2012 ◽  
Vol 2 (1) ◽  
Author(s):  
Mohammad Khan ◽  
Abdul Ansari
Keyword(s):  
Power Consumption ◽  
Clock Cycle ◽  
Network On Chip ◽  
Fixed Number ◽  
Clock Frequency ◽  
Mesh Topology ◽  
Communication Technique ◽  
Ip Cores ◽  
On Chip ◽  
Area Efficient

AbstractThe Network-on-Chip (NoC) is an emerging communication technique for System-on-Chip (SoC) communications. The NoC uses multiple processors, usually targeted for embedded applications and other applications [3, 13]. Performance of the bus is degraded by the increasing number of processing elements and transaction oriented model [13]. This has attracted much attention for applying wireless network protocols as CDMA, TDMA, and dTDMA in SoC. The TDMA systems use a fixed number of timeslots. This protocol wastes bandwidth when some timeslots are allocated but not used. The dynamic TDMA (dTDMA) bus arbiter dynamically grows and shrinks the number of timeslots to match the number of active transmitters [14]. In this paper, we present a design of area-efficient switch for inter-layer communications in 3-D NoC. The arbitration logic in the switch is based on a programmable priority encoder. A 640-bit message with uniform random destination data pattern was injected per IP per machine clock cycle. We have obtained the maximum clock frequency of 2.09 GHz for 96(4 × 8 × 3) IP cores connected in a mesh topology. The presented architecture demonstrates their superior functionality in terms of speed, latency, area, and power consumption as compared with the existing implementation [14]. The maximum power consumption of the proposed area-efficient programmable arbiter is 0.625 mW. The design is synthesized using 180nm TSMC Technology.

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