A PLL clock frequency multiplier using dynamic current matching adaptive charge-pump and VCO frequency reuse

2007 ◽  
Vol 12 (3) ◽  
pp. 491-495
Author(s):  
Tao Zhang ◽  
Xuecheng Zou ◽  
Guangzhou Zhao ◽  
Xubang Shen
Keyword(s):  
Charge Pump ◽  
Frequency Multiplier ◽  
Frequency Reuse ◽  
Clock Frequency ◽  
Current Matching

scholarly journals Phase Frequency Detector and Charge Pump for Low Jitter PLL Applications

2018 ◽  
Vol 8 (6) ◽  
pp. 4120
Author(s):  
Sung Sik Park ◽  
Ju Sang Lee ◽  
Sang Dae Yu
Keyword(s):  
Circuit Simulation ◽  
Pulse Height ◽  
Charge Pump ◽  
Cmos Process ◽  
Charge Pumps ◽  
Current Matching ◽  
Low Jitter ◽  
A New Technique ◽  
Charge Pump Circuit ◽  
Frequency Detector

In this paper a new technique is presented to improve the jitter performance of conventional phase frequency detectors by completely removing the unnecessary one-shot pulse. This technique uses a variable pulse-height circuit to control the unnecessary one-shot pulse height. In addition, a novel charge-pump circuit with perfect current-matching characteristics is used to improve the output jitter performance of conventional charge pumps. This circuit is composed of a pair of symmetrical pump circuits to obtain a good current matching. As a result, the proposed charge-pump circuit has perfect current-matching characteristics, wide output range, no glitch output current, and no jump output voltage. In order to verify such operation, circuit simulation is performed using 0.18 μm CMOS process parameters.

scholarly journals New Discrete Fibonacci Charge Pump Design, Evaluation and Measurement

2017 ◽  
Vol 17 (3) ◽  
pp. 100-107 ◽  
Author(s):  
David Matoušek ◽  
Jiří Hospodka ◽  
Ondřej Šubrt
Keyword(s):  
Printed Circuit Board ◽  
Charge Pump ◽  
Circuit Board ◽  
Design Evaluation ◽  
Clock Frequency ◽  
Pump Design ◽  
Charge Pumps ◽  
Printed Circuit ◽  
Variable Power ◽  
Charge Pump Circuit

AbstractThis paper focuses on the practical aspects of the realisation of Dickson and Fibonacci charge pumps. Standard Dickson charge pump circuit solution and new Fibonacci charge pump implementation are compared. Both charge pumps were designed and then evaluated by LTspice XVII simulations and realised in a discrete form on printed circuit board (PCB). Finally, the key parameters as the output voltage, efficiency, rise time, variable power supply and clock frequency effects were measured.

Fast-Transient-Response Low-Voltage Integrated, Interleaved DC–DC Converter for Implantable Devices

2019 ◽  
Vol 29 (01) ◽  
pp. 2050013
Author(s):  
Najmeh Cheraghi Shirazi ◽  
Abumoslem Jannesari ◽  
Pooya Torkzadeh
Keyword(s):  
Power Consumption ◽  
Transient Response ◽  
Output Voltage ◽  
Low Voltage ◽  
Charge Pump ◽  
Input Voltage ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Voltage Ripple ◽  
Body Biasing

A new self-start-up switched-capacitor charge pump is proposed for low-power, low-voltage and battery-less implantable applications. To minimize output voltage ripple and improve transient response, interleaving regulation technique is applied to a multi-stage Cross-Coupled Charge Pump (CCCP) circuit. It splits the power flow in a time-sequenced manner. Three cases of study are designed and investigated with body-biasing technique by auxiliary transistors: Four-stage Two-Branch CCCP (TBCCCP), the two-cell four-stage Interleaved Two-Branch CCCP (ITBCCCP2) and four-cell four-stage Interleaved Two-Branch CCCP (ITBCCCP4). Multi-phase nonoverlap clock generator circuit with body-biasing technique is also proposed which can operate at voltages as low as CCCP circuits. The proposed circuits are designed with input voltage as low as 300 to 400[Formula: see text]mV and 20[Formula: see text]MHz clock frequency for 1[Formula: see text]pF load capacitance. Among the three designs, ITBCCCP4 has the lowest ramp-up time (41.6% faster), output voltage ripple (29% less) and power consumption (19% less). The Figure-Of-Merit (FOM) of ITBCCCP4 is the highest value among two others. For 400[Formula: see text]mV input voltage, ITBCCCP4 has a 98.3% pumping efficiency within 11.6[Formula: see text][Formula: see text]s, while having a maximum voltage ripple of 0.1% and a power consumption as low as 2.7[Formula: see text]nW. The FOM is 0.66 for this circuit. The designed circuits are implemented in 180-nm standard CMOS technology with an effective chip area of [Formula: see text][Formula: see text][Formula: see text]m for TBCCCP, [Formula: see text][Formula: see text][Formula: see text]m for ITBCCCP2 and [Formula: see text][Formula: see text][Formula: see text]m for ITBCCCP4.

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