scholarly journals Simultaneous Multi-AUV Operation as Real Practice - High-efficiency and High-definition Bottom Survey in Izu Islands

2021 ◽  
Vol 56 (1) ◽  
pp. 132-138
Author(s):  
Kangsoo Kim ◽  
Takumi Sato ◽  
Shogo Inaba ◽  
Atsuo Oono ◽  
Takeya Matsuda ◽  
...  
Keyword(s):  
High Efficiency ◽  
High Definition ◽  
Real Practice ◽  
Izu Islands

scholarly journals Robust and fast selective encryption for HEVC videos

2014 ◽  
Vol 10 (4) ◽  
pp. 221 ◽  
Author(s):  
Mokhtar Ouamri ◽  
Kamel M. Faraoun
Keyword(s):  
High Efficiency ◽  
Operating Mode ◽  
Advanced Encryption Standard ◽  
Selective Encryption ◽  
High Efficiency Video Coding ◽  
High Definition ◽  
Network Applications ◽  
Encryption Schemes ◽  
Visual Degradation ◽  
Reliability And Robustness

Emerging High efficiency video coding (HEVC) is expected to be widely adopted in network applications for high definition devices and mobile terminals. Thus, construction of HEVC's encryption schemes that maintain format compliance and bit rate of encrypted bitstream becomes an active security's researches area. This paper presents a novel selective encryption technique for HEVC videos, based on enciphering the bins of selected Golomb–Rice code’s suffixes with the Advanced Encryption Standard (AES) in a CBC operating mode. The scheme preserves format compliance and size of the encrypted HEVC bitstream, and provides high visual degradation with optimized encryption space defined by selected Golomb–Rice suffixes. Experimental results show reliability and robustness of the proposed technique.

scholarly journals Quality-Oriented Perceptual HEVC Based on the Spatiotemporal Saliency Detection Model

Entropy ◽  
2019 ◽  
Vol 21 (2) ◽  
pp. 165 ◽  
Author(s):  
Xiantao Jiang ◽  
Tian Song ◽  
Daqi Zhu ◽  
Takafumi Katayama ◽  
Lu Wang
Keyword(s):  
Video Coding ◽  
High Efficiency ◽  
Saliency Detection ◽  
Saliency Map ◽  
High Efficiency Video Coding ◽  
High Definition ◽  
Perceptual Coding ◽  
Coding Scheme ◽  
Saliency Model ◽  
Video Saliency

Perceptual video coding (PVC) can provide a lower bitrate with the same visual quality compared with traditional H.265/high efficiency video coding (HEVC). In this work, a novel H.265/HEVC-compliant PVC framework is proposed based on the video saliency model. Firstly, both an effective and efficient spatiotemporal saliency model is used to generate a video saliency map. Secondly, a perceptual coding scheme is developed based on the saliency map. A saliency-based quantization control algorithm is proposed to reduce the bitrate. Finally, the simulation results demonstrate that the proposed perceptual coding scheme shows its superiority in objective and subjective tests, achieving up to a 9.46% bitrate reduction with negligible subjective and objective quality loss. The advantage of the proposed method is the high quality adapted for a high-definition video application.

Research on Key Algorithm of a New Generation Video Coding Standard HEVC

2013 ◽  
Vol 446-447 ◽  
pp. 961-965
Author(s):  
Gang Wang ◽  
He Xin Chen ◽  
Mian Shu Chen ◽  
Yuan Yuan Liu
Keyword(s):  
Video Coding ◽  
High Efficiency ◽  
Orthogonal Transformation ◽  
Basic Structure ◽  
Research Direction ◽  
Coding System ◽  
High Efficiency Video Coding ◽  
High Definition ◽  
High Definition Television ◽  
New Generation

The video coding standard of a new generation, high efficiency video coding ( HEVC ), is a video coding standard of JCT-VT under planning, mainly orienting toward high definition television （HDTV）and video coding system. From the start of the basic structure of HEVC, this paper not only introduces comprehensively the key HEVC technologies in intra-frame and inter-frame predictive estimation, orthogonal transformation, filter compensation and entropy coding but also points out the hot issues and the latest research direction.

scholarly journals FPGA-based implementation of intra prediction module for HEVC decoder

2019 ◽  
Vol 8 (2) ◽  
pp. 6130-6137
Keyword(s):  
Power Consumption ◽  
High Efficiency ◽  
Cmos Technology ◽  
Intra Prediction ◽  
Hardware Architecture ◽  
Video Frame ◽  
High Efficiency Video Coding ◽  
High Definition ◽  
Prediction Module ◽  
Block Sizes

The High Efficiency Video Coding (HEVC) is the new standard which is designed to support High Definition (HD) and Ultra-HD video cotenants. In HEVC, several new coding tools are adopted in order to improve the coding efficiency and compression ratio but with a significant increase in the computational complexity comparing to the previous standard H.264/AVC. In this paper, we focus on reducing the complexity of the most consuming block in the HEVC decoder standard which is the intra prediction module. In this context, we propose an optimized hardware architecture dedicated to support the 34 modes of intra prediction module considering 4×4, 8×8 and 16×16 block sizes. The proposed design exploits the symmetric property between horizontal and vertical modes. Hence, we implement a new hardware architecture that factorizes the same hardware resources for both directions which leads to save the hardware cost, the power consumption and the processing time. Furthermore, the different block sizes are implemented independently in order to avoid memory overhead while accessing to the shared memory. The implemented design using Xilinx Zynq-based FPGA platform can process in real time the Ultra-HD video frame of resolution (4096×2048) at 232 MHz. As well, the synthesis results using the TSMC 180 nm CMOS technology provide similar performance than our FPGA implementation. Finally, the HW/SW implementation of full HEVC decoder can process the decoding of 15 FPS in best case for 240p video resolution with a gain of 60% in power consumption.

scholarly journals Block Based Enhancement using Deep Learning for Conversion of Low Resolution AVS Video to High Resolution HEVC Video

2021 ◽  
Author(s):  
Rizwan Qureshi ◽  
Mehmood Nawaz
Keyword(s):  
Deep Learning ◽  
High Efficiency ◽  
Motion Vector ◽  
Super Resolution ◽  
Computational Time ◽  
Video Frame ◽  
Low Resolution ◽  
High Efficiency Video Coding ◽  
High Definition ◽  
Resolution Method

Conversion of one video bitstream to another video bitstream is a challenging task in the heterogeneous transcoder due to different video formats. In this paper, a region of interest (ROI) based super resolution technique is used to convert the lowresolution AVS (audio video standard) video to high definition HEVC (high efficiency video coding) video. Firstly, we classify a low-resolution video frame into small blocks by using visual characteristics, transform coefficients, and motion vector (MV) of a video. These blocks are further classified as blocks of most interest (BOMI), blocks of less interest (BOLI) and blocks of noninterest (BONI). The BONI blocks are considered as background blocks due to less interest in video and remains unchanged during SR process. Secondly, we apply deep learning based super resolution method on low resolution BOMI, and BOLI blocks to enhance the visual quality. The BOMI and BOLI blocks have high attention due to ROI that include some motion and contrast of the objects. The proposed method saves 20% to 30% computational time and obtained appreciable results as compared with full frame based super resolution method. We have tested our method on different official video sequences with resolution of 1K, 2K, and 4K. Our proposed method has an efficient visual performance in contrast to the full frame-based super resolution method.

FPGA-Based ROI Encoding for HEVC Video Bitrate Reduction

2020 ◽  
Vol 29 (11) ◽  
pp. 2050182
Author(s):  
Zhilei Chai ◽  
Shen Li ◽  
Qunfang He ◽  
Mingsong Chen ◽  
Wenjie Chen
Keyword(s):  
Data Storage ◽  
Video Compression ◽  
High Efficiency ◽  
Video Quality ◽  
Region Of Interest ◽  
Absolute Difference ◽  
High Efficiency Video Coding ◽  
High Definition ◽  
Mapping Algorithm ◽  
Block Based

The explosive growth of video applications has produced great challenges for data storage and transmission. In this paper, we propose a new ROI (region of interest) encoding solution to accelerate the processing and reduce the bitrate based on the latest video compression standard H.265/HEVC (High-Efficiency Video Coding). The traditional ROI extraction mapping algorithm uses pixel-based Gaussian background modeling (GBM), which requires a large number of complex floating-point calculations. Instead, we propose a block-based GBM to set up the background, which is in accord with the block division of HEVC. Then, we use the SAD (sum of absolute difference) rule to separate the foreground block from the background block, and these blocks are mapped into the coding tree unit (CTU) of HEVC. Moreover, the quantization parameter (QP) is adjusted according to the distortion rate automatically. The experimental results show that the processing speed on FPGA has reached a real-time level of 22 FPS (frames per second) for full high-definition videos ([Formula: see text]), and the bitrate is reduced by 10% on average with stable video quality.

Analysis of Deep Rain Streaks Removal Convolutional Neural Network-Based Post-Processing Techniques in HEVC Encoder

2020 ◽  
pp. 2150020
Author(s):  
Thiyagarajan Jayaraman ◽  
Gowri Shankar Chinnusamy
Keyword(s):  
Neural Network ◽  
Convolutional Neural Network ◽  
Optimization Algorithm ◽  
High Efficiency ◽  
Convergence Time ◽  
Video Sequences ◽  
Bit Rate ◽  
Post Processing ◽  
Rate Reduction ◽  
High Definition

This paper presents Deep Rain Streaks Removal Convolutional Neural Network (Derain SRCNN) based post-processing optimization algorithm for High-Efficiency Video Coder (HEVC). Earlier, the CNN-based denoising optimization algorithm faced overfitting issues and large convergence time when training the CNN for rain streaks affected High Definition (HD) video sequences. To address these problems, Deep rain streaks removal CNN-based post-processing block is introduced in HEVC encoder. Derain SRCNN architecture consists of a parallel two residual block layer and Dual Channel Rectification Linear Unit (DCReLU) activation function with various sizes of the convolutional layer. By reducing the validate error and training the error of CNN, the overfitting issue is solved. Also, convergence time is reduced using proper learning rate and kernel weight of optimization algorithm. The proposed network provides a higher bit rate reduction and higher convergence speed for corrupted high-definition video sequences. The experiment result shows that proposed DerainSRCNN-based post-processing filtering method achieves 6.8% and 4.1% -bit rate reduction for random access (RA) and low delay [Formula: see text] frame (LDP) configuration, respectively.

scholarly journals Motion Estimation in HEVC/H.265: Metaheuristic Approach to Improve the Efficiency

2021 ◽  
Vol 12 (1) ◽  
pp. 59
Author(s):  
Khwaja Humble Hassan ◽  
Shahzad Ahmad Butt
Keyword(s):  
Motion Estimation ◽  
Video Coding ◽  
High Efficiency ◽  
Optimization Problems ◽  
Search Algorithm ◽  
High Efficiency Video Coding ◽  
High Definition ◽  
The Social ◽  
Test Zone ◽  
Encoding Efficiency

An ever increasing use of digital video applications such as video telephony, broadcast and the storage of high and ultra-high definition videos has steered the development of video coding standards. The state of the art video coding standard is High Efficiency Video Coding (HEVC) or otherwise known as H.265. It promises to be 50 percent more efficient than the previous video coding standard H.264. Ultimately, H.265 provides significant improvement in compression at the expense of computational complexity. HEVC encoder is very complex and 50 percent of the encoding consists of Motion Estimation (ME). It uses a Test Zone (TZ) fast search algorithm for its motion estimation, which compares a block of pixels with a few selected blocks in the search region of a referenced frame. However, the encoding time is not suitable to meet the needs of real time video applications. So, there is a requirement to improve the search algorithm and to provide comparable results to TZ search to save a substantial amount of time. In our paper, we aim to study the effects of a meta-heuristic algorithm on motion estimation. One such suitable algorithm for this task is the Firefly Algorithm (FA). FA is inspired by the social behavior of fireflies and is generally used to solve optimization problems. Our results show that implementing FA for ME saves a considerable amount of time with a comparable encoding efficiency.

scholarly journals Hardware Implementation for the HEVC Fractional Motion Estimation Targeting Real-Time and Low-Energy

2016 ◽  
Vol 11 (2) ◽  
pp. 106-120 ◽  
Author(s):  
Vladimir Afonso ◽  
Henrique Maich ◽  
Luan Audibert ◽  
Bruno Zatt ◽  
Marcelo Porto ◽  
...  
Keyword(s):  
Motion Estimation ◽  
High Efficiency ◽  
Hardware Design ◽  
Resource Usage ◽  
High Efficiency Video Coding ◽  
High Definition ◽  
Energy Aware ◽  
Hardware Resource ◽  
High Processing ◽  
Fractional Motion Estimation

This paper presents an energy-aware and high-throughput hardware design for the Fractional Motion Estimation (FME) compliant with the High Efficiency Video Coding (HEVC) standard. An extensive software evaluation was performed to guide the hardware design. The adopted strategy mainly consists in using only the four squareshaped Prediction Unit (PU) sizes rather than using all 24 possible PU sizes in the Motion Estimation (ME). This approach reduces about 59% the total encoding time and, as a penalty, it leads to an increase of only 4% in the bit rate for the same image quality. Together with this simplification, a multiplierless approach, algebraic optimizations and low-power techniques were applied to the hardware design to reduce the hardware-resource usage and the energy consumption, maintaining a high processing rate. The architecture was described in VHDL and the synthesis results for ASIC 45nm Nangate standard cells demonstrate that the developed architecture is able to process Ultra-High Definition (UHD) 2160p videos at 60 frames per second (fps), with the lowest power consumption and the lowest hardware-resource usage among the related works.

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