A comparative study on off-state breakdown characteristics in nanowire JL and IM multiple gate MOSFETs has been performed for different gate bias voltages and fin widths. In order to understand the drain breakdown mechanism with different transistor structures, the device was simulated using the 3-dimensional ATLAS software. The band-to-band tunneling current and the gate-induced-drain-leakage current trigger the off-state breakdown in JL transistor and IM transistor, respectively. From experiment and simulation, the off-state breakdown voltage is lower in JL transistor than in IM transistor. As the gate is biased more negatively, the off-state breakdown voltages are increased in JL and IM transistors.
Comparative Analysis of PBTI Induced Device Degradation in Junctionless and Inversion Mode Multiple-Gate MOSFET
