Accumulation-mode and inversion-mode triple-gate MOSFETs

2008 ◽  
Author(s):  
R. Yan ◽  
A. Afzalian ◽  
C.-W. Lee ◽  
D.N. Akhavan ◽  
W. Xiong ◽  
...  
Keyword(s):  
Inversion Mode ◽  
Accumulation Mode ◽  
And Inversion

Achieving Reduced Specific On-Resistance in 1.2 kV SiC Power MOSFETs at Elevated Temperature

2019 ◽  
Vol 963 ◽  
pp. 588-591
Author(s):  
Ki Jeong Han ◽  
B. Jayant Baliga
Keyword(s):  
Elevated Temperatures ◽  
Structural Parameters ◽  
Analytical Models ◽  
Power Mosfets ◽  
Inversion Mode ◽  
Accumulation Mode ◽  
Ambient Temperatures ◽  
Lower Ratio ◽  
And Inversion ◽  
The Impact

Power MOSFETs operate at elevated temperatures due to self-heating and hot ambient temperatures. This paper analyzes the increase in on-resistance with temperature for 1.2 kV rated 4H-SiC planar MOSFETs. The impact of various structural parameters are studied using analytical models supported by experimental data. This work defines how to achieve a low ratio [Ron(150°C)/Ron(25°C)] by structural optimization of 1.2 kV SiC planar MOSFETs for the first time. It is found that the inversion mode MOSFETs, fabricated by us in a 6 inch commercial foundry, have a lower ratio [Ron(150°C)/Ron(25°C)] than the accumulation mode MOSFETs, due to a better balance of change in channel and bulk mobility with temperature. Compared with typical commercially available MOSFETs, our fabricated accumulation mode and inversion mode MOSFETs exhibit a lower ratio [Ron(150°C)/Ron(25°C)], resulting in superior HF-FOM [RonxQgd] at 150°C.

Comparative Studies of Furnace and Rapid Thermal Passivation for Accumulation and Inversion Mode Polysilicon-On-Oxide Mosfets.

1990 ◽  
Vol 182 ◽  
Author(s):  
S. Batra ◽  
K. Park ◽  
S. Banerjee ◽  
R. Sundaresan
Keyword(s):  
Grain Boundary ◽  
Barrier Height ◽  
Atomic Hydrogen ◽  
Carrier Transport ◽  
Inversion Mode ◽  
Accumulation Mode ◽  
Potential Barriers ◽  
And Inversion ◽  
Channel Region ◽  
Grain Boundary Barrier

AbstractCarrier transport in the channel region of polysilicon thin film MOSFETs is affected by the presence of grain boundary potential barriers and is further complicated by the modulation of the grain boundary barrier height with gate voltage. Passivation of the trap sites with atomic hydrogen reduces the barrier height and thereby improves the performance of polysilicon transistors. In this paper, we demonstrate the effectiveness of Rapid Thermal Annealing (RTA) using Si3N4 as a solid source of H as a passivation technique for both inversion and accumulation mode polysilicon MOSFETs. ON/OFF ratios of 107 can be obtained by RTA passivation for inversion mode polysilicon MOSFETs compared to 106 after furnace passivation permitting the potential application of these MOSFETs both as load transistors in SRAMs as well as pass transistors in DRAMs. In contrast, the ON&OFF ratio of accumulation mode polysilicon MOSFETs does not show any improvement even though ID and VT improve with passivation. This is because of excessive back channel leakage in accumulation mode MOSFETs which increases with passivation.

Comparison of contact resistance between accumulation-mode and inversion-mode multigate FETs

2008 ◽  
Vol 52 (11) ◽  
pp. 1815-1820 ◽  
Author(s):  
Chi-Woo Lee ◽  
Dimitri Lederer ◽  
Aryan Afzalian ◽  
Ran Yan ◽  
Nima Dehdashti ◽  
...  
Keyword(s):  
Contact Resistance ◽  
Inversion Mode ◽  
Accumulation Mode ◽  
And Inversion

Reduction of Variability in Junctionless and Inversion-Mode FinFETs by Stringer Gate Structure

2018 ◽  
Vol 65 (2) ◽  
pp. 470-475 ◽  
Author(s):  
Jungsik Kim ◽  
Jin-Woo Han ◽  
M. Meyyappan
Keyword(s):  
Inversion Mode ◽  
Gate Structure ◽  
And Inversion

Comparative Study on Off-State Breakdown Characteristics in Nanowire Junctionless and Inversion Mode Multiple Gate MOSFET

2013 ◽  
Vol 684 ◽  
pp. 295-298
Author(s):  
Seung Min Lee ◽  
Hyun Jun Jang ◽  
Jong Tae Park
Keyword(s):  
Comparative Study ◽  
Leakage Current ◽  
Tunneling Current ◽  
Gate Bias ◽  
Inversion Mode ◽  
3 Dimensional ◽  
Breakdown Mechanism ◽  
Band To Band Tunneling ◽  
State Breakdown ◽  
And Inversion

A comparative study on off-state breakdown characteristics in nanowire JL and IM multiple gate MOSFETs has been performed for different gate bias voltages and fin widths. In order to understand the drain breakdown mechanism with different transistor structures, the device was simulated using the 3-dimensional ATLAS software. The band-to-band tunneling current and the gate-induced-drain-leakage current trigger the off-state breakdown in JL transistor and IM transistor, respectively. From experiment and simulation, the off-state breakdown voltage is lower in JL transistor than in IM transistor. As the gate is biased more negatively, the off-state breakdown voltages are increased in JL and IM transistors.

Extraction of series resistance on junctionless and inversion-mode nanowire FET through the method based on Y-function

2013 ◽  
Author(s):  
Chan-Hoon Park ◽  
Myung-Dong Ko ◽  
Ki-Hyun Kim ◽  
Jae-Ho Hong ◽  
Rock-Hyun Baek ◽  
...  
Keyword(s):  
Series Resistance ◽  
Inversion Mode ◽  
And Inversion
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